📄 turbo_code_no_punc.mdl
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seed "Seed"
}
Block {
BlockType Reference
Name "Random\nInterleaver3"
Ports [1, 1]
Position [290, 172, 340, 228]
Orientation "left"
NamePlacement "alternate"
SourceBlock "commblkintrlv2/Random\nInterleaver"
SourceType "Random Interleaver"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
N "Len"
seed "Seed"
}
Block {
BlockType Terminator
Name "Terminator1"
Position [460, 200, 480, 220]
}
Block {
BlockType Terminator
Name "Terminator2"
Position [70, 225, 90, 245]
Orientation "left"
NamePlacement "alternate"
}
Block {
BlockType Outport
Name "Out1"
Position [25, 43, 55, 57]
Orientation "left"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "APP Decoder1"
SrcPort 1
Points [0, 0]
DstBlock "Random\nDeinterleaver"
DstPort 1
}
Line {
SrcBlock "APP Decoder"
SrcPort 2
Points [0, 20]
DstBlock "Terminator1"
DstPort 1
}
Line {
SrcBlock "APP Decoder1"
SrcPort 2
Points [0, -5]
DstBlock "Terminator2"
DstPort 1
}
Line {
SrcBlock "Random\nDeinterleaver"
SrcPort 1
Points [0, -15; 30, 0]
Branch {
DstBlock "Delay"
DstPort 1
}
Branch {
DstBlock "Hard Decision1"
DstPort 1
}
}
Line {
SrcBlock "Random\nInterleaver3"
SrcPort 1
DstBlock "APP Decoder1"
DstPort 1
}
Line {
SrcBlock "APP Decoder"
SrcPort 1
Points [0, 10]
DstBlock "Random\nInterleaver3"
DstPort 1
}
Line {
SrcBlock "Frame Reset"
SrcPort 1
DstBlock "APP Decoder"
DstPort 1
}
Line {
SrcBlock "Delay"
SrcPort 1
Points [0, 0]
DstBlock "Frame Reset"
DstPort 1
}
Line {
SrcBlock "Discrete Pulse\nGenerator"
SrcPort 1
Points [10, 0; 0, -20]
DstBlock "Frame Reset"
DstPort 2
}
Line {
SrcBlock "Hard Decision1"
SrcPort 1
Points [0, 0]
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
Points [0, 0]
DstBlock "APP Decoder"
DstPort 2
}
Line {
SrcBlock "In2"
SrcPort 1
Points [0, 0]
DstBlock "APP Decoder1"
DstPort 2
}
}
}
Block {
BlockType SubSystem
Name "turbo_encoder"
Ports [1, 1]
Position [330, 130, 405, 190]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "turbo_encoder"
Location [105, 97, 944, 443]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [25, 48, 55, 62]
IconDisplay "Port number"
}
Block {
BlockType Reference
Name "Convolutional\nEncoder"
Ports [1, 1]
Position [220, 25, 340, 85]
SourceBlock "commcnvcod2/Convolutional\nEncoder"
SourceType "Convolutional Encoder"
trellis "trellis"
opMode "Continuous"
usePuncVector off
punctureVector "[ 1 1 0 1 0 1]'"
reset "Unused parameter value"
}
Block {
BlockType Reference
Name "Convolutional\nEncoder1"
Ports [1, 1]
Position [225, 120, 345, 180]
SourceBlock "commcnvcod2/Convolutional\nEncoder"
SourceType "Convolutional Encoder"
trellis "trellis"
opMode "Truncated (reset every frame)"
usePuncVector off
punctureVector "[ 1 1 0 1 0 1]'"
reset "Unused parameter value"
}
Block {
BlockType Reference
Name "Deinterlacer"
Ports [1, 2]
Position [375, 43, 455, 92]
SourceBlock "commsequence2/Deinterlacer"
SourceType "Deinterlacer"
}
Block {
BlockType Reference
Name "Deinterlacer1"
Ports [1, 2]
Position [375, 123, 455, 172]
SourceBlock "commsequence2/Deinterlacer"
SourceType "Deinterlacer"
}
Block {
BlockType Reference
Name "Matrix\nConcatenate"
Ports [3, 1]
Position [540, 61, 590, 119]
SourceBlock "simulink_obsolete/Matrix\nConcatenation"
SourceType "Matrix Concatenation"
numInports "3"
catMethod "Vertical"
}
Block {
BlockType Reference
Name "Random\nInterleaver"
Ports [1, 1]
Position [125, 123, 205, 177]
SourceBlock "commblkintrlv2/Random\nInterleaver"
SourceType "Random Interleaver"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
N "Len"
seed "Seed"
}
Block {
BlockType Terminator
Name "Terminator3"
Position [480, 125, 500, 145]
}
Block {
BlockType Reference
Name "Unipolar to\nBipolar\nConverter"
Ports [1, 1]
Position [720, 62, 755, 118]
NamePlacement "alternate"
SourceBlock "commutil2/Unipolar to\nBipolar\nConverter"
SourceType "Unipolar to Bipolar Converter"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
M "2"
polarity "Positive"
dataType "double"
}
Block {
BlockType Reference
Name "read from \ncolumn to row"
Ports [1, 1]
Position [615, 63, 695, 117]
SourceBlock "commblkintrlv2/Matrix\nInterleaver"
SourceType "Matrix Interleaver"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Nrows "3"
Ncols "Len"
}
Block {
BlockType Outport
Name "encoded"
Position [780, 83, 810, 97]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "In1"
SrcPort 1
Points [0, 0; 15, 0]
Branch {
DstBlock "Convolutional\nEncoder"
DstPort 1
}
Branch {
Labels [2, 0]
Points [0, 95]
DstBlock "Random\nInterleaver"
DstPort 1
}
}
Line {
SrcBlock "Unipolar to\nBipolar\nConverter"
SrcPort 1
Points [0, 0]
DstBlock "encoded"
DstPort 1
}
Line {
SrcBlock "Random\nInterleaver"
SrcPort 1
DstBlock "Convolutional\nEncoder1"
DstPort 1
}
Line {
SrcBlock "Convolutional\nEncoder"
SrcPort 1
Points [15, 0]
DstBlock "Deinterlacer"
DstPort 1
}
Line {
SrcBlock "Convolutional\nEncoder1"
SrcPort 1
Points [0, 0]
DstBlock "Deinterlacer1"
DstPort 1
}
Line {
SrcBlock "Deinterlacer1"
SrcPort 1
Points [0, 0]
DstBlock "Terminator3"
DstPort 1
}
Line {
SrcBlock "Deinterlacer"
SrcPort 1
Points [30, 0; 0, 15]
DstBlock "Matrix\nConcatenate"
DstPort 1
}
Line {
SrcBlock "Deinterlacer"
SrcPort 2
Points [15, 0; 0, 10]
DstBlock "Matrix\nConcatenate"
DstPort 2
}
Line {
SrcBlock "Deinterlacer1"
SrcPort 2
Points [65, 0]
DstBlock "Matrix\nConcatenate"
DstPort 3
}
Line {
SrcBlock "read from \ncolumn to row"
SrcPort 1
DstBlock "Unipolar to\nBipolar\nConverter"
DstPort 1
}
Line {
SrcBlock "Matrix\nConcatenate"
SrcPort 1
Points [0, 0]
DstBlock "read from \ncolumn to row"
DstPort 1
}
}
}
Line {
SrcBlock "Multiple Error Rate Calculation1"
SrcPort 1
DstBlock "Display"
DstPort 1
}
Line {
SrcBlock "turbo_decoder"
SrcPort 1
Points [-95, 0]
DstBlock "Multiple Error Rate Calculation1"
DstPort 2
}
Line {
Labels [0, 0]
SrcBlock "Bernoulli Binary\nGenerator"
SrcPort 1
Points [25, 0]
Branch {
DstBlock "turbo_encoder"
DstPort 1
}
Branch {
Points [0, 115]
DstBlock "Multiple Error Rate Calculation1"
DstPort 1
}
}
Line {
SrcBlock "receiver_front_end"
SrcPort 1
DstBlock "turbo_decoder"
DstPort 1
}
Line {
SrcBlock "receiver_front_end"
SrcPort 2
DstBlock "turbo_decoder"
DstPort 2
}
Line {
SrcBlock "turbo_encoder"
SrcPort 1
Points [145, 0]
DstBlock "AWGN\nChannel"
DstPort 1
}
Line {
SrcBlock "AWGN\nChannel"
SrcPort 1
Points [0, 155]
DstBlock "receiver_front_end"
DstPort 1
}
Annotation {
Position [39, 50]
UseDisplayTextAsClickCallback off
}
Annotation {
Name "A turbo code simulation\nIn Soo Ahn\nDept. of E"
"lectrical and Computer Engineering\nBradley University\nPeoria, IL 61625"
Position [372, 68]
ForegroundColor "blue"
DropShadow on
UseDisplayTextAsClickCallback off
FontSize 14
}
Annotation {
Name "generator polynomials\nG1 = [1 1 1 1 1] \nG2 = "
"[1 0 0 0 1]\nNo puncturing (code rate 1/3)"
Position [651, 69]
UseDisplayTextAsClickCallback off
FontSize 16
}
}
}
MatData {
NumRecords 2
DataRecord {
Tag DataTag1
Data " %)30 . 8 8 ( 0 % "
"\" $ ! 0 . , 8 ( ! % \" $ "
"$ 0 0 0 365A;@"
}
DataRecord {
Tag DataTag0
Data " %)30 . > 8 ( 0 % "
"\" $ ! 0 . 2 8 ( ! % \" $ "
"2 0 0 $@ $)E<FYO=6QL:4)I;F%R>4=E;@ "
}
}
# Finite State Machines
#
# Stateflow Version 6.5 (R2006b) dated Aug 8 2006, 21:09:58
#
#
Stateflow {
machine {
id 1
name "turbo_code_no_punc"
created "22-Nov-2006 17:46:50"
isLibrary 0
firstTarget 2
sfVersion 65014000
}
target {
id 2
name "sfun"
description "Default Simulink S-Function Target."
machine 1
linkNode [1 0 0]
}
}
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