tigon3.c

PPC Linux Driver, use makefile to compare the routen in Linux.

    Value32 &= ~T3_PM_POWER_STATE_MASK;
    Value32 |= T3_PM_POWER_STATE_D0;
    MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32);

    /* read the current PCI command word */
    MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);

    /* Make sure bus-mastering is enabled. */
    Value32 |= PCI_BUSMASTER_ENABLE;

#if PCIX_TARGET_WORKAROUND
    /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR#
        are enabled */
    if (pDevice->EnablePciXFix == TRUE) {
        Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE | 
                    PCI_PARITY_ERROR_ENABLE);
    }
    if (pDevice->UndiFix)
    {
        Value32 &= ~PCI_MEM_SPACE_ENABLE;
    }

#endif

    if(pDevice->EnableMWI)
    {
        Value32 |= PCI_MEMORY_WRITE_INVALIDATE;
    }
    else {
        Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE);
    }

    /* Error out if mem-mapping is NOT enabled for PCI systems */
    if (!(Value32 | PCI_MEM_SPACE_ENABLE))
    {
        return LM_STATUS_FAILURE;
    }

    /* save the value we are going to write into the PCI command word */	
    pDevice->PciCommandStatusWords = Value32;	

    Status = MM_WriteConfig32(pDevice, PCI_COMMAND_REG, Value32);
    if(Status != LM_STATUS_SUCCESS)
    {
        return Status;
    }

    /* Set power state to D0. */
    LM_SetPowerState(pDevice, LM_POWER_STATE_D0);

#ifdef BIG_ENDIAN_PCI
    pDevice->MiscHostCtrl = 
        MISC_HOST_CTRL_MASK_PCI_INT | 
        MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
        MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
        MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
#else /* No CPU Swap modes for PCI IO */
    
    /* Setup the mode registers. */
    pDevice->MiscHostCtrl = 
        MISC_HOST_CTRL_MASK_PCI_INT | 
        MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | 
#ifdef BIG_ENDIAN_HOST
        MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP |  
#endif /* BIG_ENDIAN_HOST */
        MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
        MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
#endif /* !BIG_ENDIAN_PCI */

    /* write to PCI misc host ctr first in order to enable indirect accesses */
    MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);

    REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl);

#ifdef BIG_ENDIAN_PCI
    Value32 = GRC_MODE_WORD_SWAP_DATA|
	      GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
#else
/* No CPU Swap modes for PCI IO */    
#ifdef BIG_ENDIAN_HOST
    Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | 
              GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
#else
    Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
#endif
#endif /* !BIG_ENDIAN_PCI */
    
    REG_WR(pDevice, Grc.Mode, Value32);

    if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
    {
        REG_WR(pDevice, Grc.LocalCtrl, GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
            GRC_MISC_LOCAL_CTRL_GPIO_OE1);
    }
    MM_Wait(40);

    /* Enable indirect memory access */
    REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);

    if (REG_RD(pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK)
    {
        REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK |
                T3_PCI_SELECT_ALTERNATE_CLOCK);
        REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_SELECT_ALTERNATE_CLOCK);
        MM_Wait(40);  /* required delay is 27usec */
    }
    REG_WR(pDevice, PciCfg.ClockCtrl, 0);
    REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0);

#if PCIX_TARGET_WORKAROUND
    MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32);
    if ((pDevice->EnablePciXFix == FALSE) &&
        ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0))
    {
        if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
            pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
            pDevice->ChipRevId == T3_CHIP_ID_5701_B2 ||
            pDevice->ChipRevId == T3_CHIP_ID_5701_B5)
        {
            __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x300]));
            __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301]));
            __raw_writel(0xffffffff, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301]));
            if (__raw_readl(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300])))
            {
                pDevice->EnablePciXFix = TRUE;
            }
        }
    }
#endif
#if 1
    /* 
    *  This code was at the beginning of else block below, but that's
    *  a bug if node address in shared memory.
    */
    MM_Wait(50);
    LM_NvramInit(pDevice);
#endif
    /* Get the node address.  First try to get in from the shared memory. */
    /* If the signature is not present, then get it from the NVRAM. */
    Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_HIGH_MAILBOX);
    if((Value32 >> 16) == 0x484b)
    {

        pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8);
        pDevice->NodeAddress[1] = (LM_UINT8) Value32;

        Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_LOW_MAILBOX);

        pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24);
        pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16);
        pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8);
        pDevice->NodeAddress[5] = (LM_UINT8) Value32;

        Status = LM_STATUS_SUCCESS;
    }
    else
    {
        Status = LM_NvramRead(pDevice, 0x7c, &Value32);
        if(Status == LM_STATUS_SUCCESS)
        {
            pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16);
            pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24);

            Status = LM_NvramRead(pDevice, 0x80, &Value32);

            pDevice->NodeAddress[2] = (LM_UINT8) Value32;
            pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8);
            pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16);
            pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24);
        }
    }

    /* Assign a default address. */
    if(Status != LM_STATUS_SUCCESS)
    {
#ifndef EMBEDDED
        printk(KERN_ERR "Cannot get MAC addr from NVRAM. Using default.\n");
#endif
        pDevice->NodeAddress[0] = 0x00; pDevice->NodeAddress[1] = 0x10;
        pDevice->NodeAddress[2] = 0x18; pDevice->NodeAddress[3] = 0x68;
        pDevice->NodeAddress[4] = 0x61; pDevice->NodeAddress[5] = 0x76;
    }

    pDevice->PermanentNodeAddress[0] = pDevice->NodeAddress[0];
    pDevice->PermanentNodeAddress[1] = pDevice->NodeAddress[1];
    pDevice->PermanentNodeAddress[2] = pDevice->NodeAddress[2];
    pDevice->PermanentNodeAddress[3] = pDevice->NodeAddress[3];
    pDevice->PermanentNodeAddress[4] = pDevice->NodeAddress[4];
    pDevice->PermanentNodeAddress[5] = pDevice->NodeAddress[5];

    /* Initialize the default values. */
    pDevice->NoTxPseudoHdrChksum = FALSE;
    pDevice->NoRxPseudoHdrChksum = FALSE;
    pDevice->NicSendBd = FALSE;
    pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT;
    pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT;
    pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS;
    pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS;
    pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES;
    pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES;
    pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
    pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
    pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
    pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
    pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS;
    pDevice->EnableMWI = FALSE;
    pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
    pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
    pDevice->DisableAutoNeg = FALSE;
    pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO;
    pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO;
    pDevice->LedMode = LED_MODE_AUTO;
    pDevice->ResetPhyOnInit = TRUE;
    pDevice->DelayPciGrant = TRUE;
    pDevice->UseTaggedStatus = FALSE;
    pDevice->OneDmaAtOnce = BAD_DEFAULT_VALUE;

    pDevice->DmaMbufLowMark = T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO;
    pDevice->RxMacMbufLowMark = T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO;
    pDevice->MbufHighMark = T3_DEF_MBUF_HIGH_WMARK_JUMBO;

    pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO;
    pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE;
    pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE;
    pDevice->EnableTbi = FALSE;
#if INCLUDE_TBI_SUPPORT
    pDevice->PollTbiLink = BAD_DEFAULT_VALUE;
#endif

    switch (T3_ASIC_REV(pDevice->ChipRevId))
    {
    case T3_ASIC_REV_5704:
        pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
        pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64;
        break;
    default:
        pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
        pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96;
        break;
    }

    pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
    pDevice->QueueRxPackets = TRUE;

    pDevice->EnableWireSpeed = TRUE;

#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
    pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */

    /* Make this is a known adapter. */
    pAdapterInfo = LM_GetAdapterInfoBySsid(pDevice->SubsystemVendorId,
        pDevice->SubsystemId);

    pDevice->BondId = REG_RD(pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK;
    if (pDevice->BondId != GRC_MISC_BD_ID_5700 &&
        pDevice->BondId != GRC_MISC_BD_ID_5701 &&
        pDevice->BondId != GRC_MISC_BD_ID_5702FE &&
        pDevice->BondId != GRC_MISC_BD_ID_5703 &&
        pDevice->BondId != GRC_MISC_BD_ID_5703S &&
        pDevice->BondId != GRC_MISC_BD_ID_5704 &&
        pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE)
    {
        return LM_STATUS_UNKNOWN_ADAPTER;
    }

    pDevice->SplitModeEnable = SPLIT_MODE_DISABLE;
    if ((pDevice->ChipRevId == T3_CHIP_ID_5704_A0) &&
        (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE))
    {
        pDevice->SplitModeEnable = SPLIT_MODE_ENABLE;
        pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ;
    }

    /* Get Eeprom info. */
    Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR);
    if (Value32 == T3_NIC_DATA_SIG)
    {
        EeSigFound = TRUE;
        Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR);

        /* Determine PHY type. */
        switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK)
        {
            case T3_NIC_CFG_PHY_TYPE_COPPER:
                EePhyTypeSerdes = FALSE;
                break;

            case T3_NIC_CFG_PHY_TYPE_FIBER:
                EePhyTypeSerdes = TRUE;
                break;

            default:
                EePhyTypeSerdes = FALSE;
                break;
        }

        /* Determine PHY led mode. */
        if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
            T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
        {
            switch(Value32 & T3_NIC_CFG_LED_MODE_MASK)
            {
                case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED:
                    EePhyLedMode = LED_MODE_THREE_LINK;
                    break;

                case T3_NIC_CFG_LED_MODE_LINK_SPEED:
                    EePhyLedMode = LED_MODE_LINK10;
                    break;

                default:
                    EePhyLedMode = LED_MODE_AUTO;
                    break;
            }
        }
        else
        {
            switch(Value32 & T3_NIC_CFG_LED_MODE_MASK)
            {
                case T3_NIC_CFG_LED_MODE_OPEN_DRAIN:
                    EePhyLedMode = LED_MODE_OPEN_DRAIN;
                    break;

                case T3_NIC_CFG_LED_MODE_OUTPUT:
                    EePhyLedMode = LED_MODE_OUTPUT;
                    break;

                default:
                    EePhyLedMode = LED_MODE_AUTO;
                    break;
            }
        }
        if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
            pDevice->ChipRevId == T3_CHIP_ID_5703_A2)
        {
            /* Enable EEPROM write protection. */
            if(Value32 & T3_NIC_EEPROM_WP)
            {
                pDevice->EepromWp = TRUE;
            }
        }

        /* Get the PHY Id. */
        Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_PHY_ID_ADDR);
        if (Value32)
        {
            EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) &
                PHY_ID1_OUI_MASK) << 10;

            Value32 = Value32 & T3_NIC_PHY_ID2_MASK;

            EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
              (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
        }
        else
        {
            EePhyId = 0;
        }
    }
    else
    {
        EeSigFound = FALSE;
    }

    /* Set the PHY address. */
    pDevice->PhyAddr = PHY_DEVICE_ID;

    /* Disable auto polling. */
    pDevice->MiMode = 0xc0000;
    REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
    MM_Wait(40);

    /* Get the PHY id. */
    LM_ReadPhy(pDevice, PHY_ID1_REG, &Value32);
    pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10;

    LM_ReadPhy(pDevice, PHY_ID2_REG, &Value32);
    pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
      (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);

    /* Set the EnableTbi flag to false if we have a copper PHY. */
    switch(pDevice->PhyId & PHY_ID_MASK)
    {
        case PHY_BCM5400_PHY_ID:
            pDevice->EnableTbi = FALSE;
            break;

        case PHY_BCM5401_PHY_ID:
            pDevice->EnableTbi = FALSE;
            break;

        case PHY_BCM5411_PHY_ID: