📄 wireless_cc1100rx.c
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count--; // update counter
} while (count != 0); // continue for <count> ms
TR0 = 0; // Stop Timer0
}
//-------------------------------------------------------------------------------------------------------
// Macro to reset the CCxxx0 and wait for it to be ready
void RESET_CCxxx0(void)
{
// SPI0CN = 0x08; // clear all flags
NSSMD0 = 0;
while (SO_data);
// {SO_data = 0;}
SPI0DAT = CCxxx0_SRES; //
SPI_WAIT();
// while (SO_data)
// {SO_data = 0;}
NSSMD0 = 1;
SO_data = 0;
}
//-------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------
// Macro to reset the CCxxx0 after power_on and wait for it to be ready
// IMPORTANT NOTICE:
// The file Wait.c must be included if this macro shall be used
// The file is located under: ..\Lib\Chipcon\Hal\CCxx00
//
// min 40 us
// <------------------>
// NSSMD0 |--| |--------------------| |-----
// | | | | |
// -- ------------
//
// MISO |----|
// -----------------------------| | |
// -- ---------
// Unknown / don't care
// SRES done
//
void POWER_UP_RESET_CCxxx0(void)
{
NSSMD0 = 1;
halWait(1);
NSSMD0 = 0;
halWait(1);
NSSMD0 = 1;
halWait(50);
RESET_CCxxx0();
}
//-------------------------------------------------------------------------------------------------------
void SPI_WAIT(void)
{
while(!SPIF);
SPIF = 0;
// SPI0CN = 0x08; // clear all flags
// CSn=0;
}
//-------------------------------------------------------------------------------------------------------
// void halWait(int timeout)
//
// DESCRIPTION:
// Runs an idle loop for [timeout] microseconds.
//
// ARGUMENTS:
// unsigned char timeout
// The timeout in microseconds
//-------------------------------------------------------------------------------------------------------
void halWait(int timeout) {
do {
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
} while (--timeout);
}// halWait
//-------------------------------------------------------------------------------------------------------
// void halSpiStrobe(BYTE strobe)
//
// DESCRIPTION:
// Function for writing a strobe command to the CCxxx0
//
// ARGUMENTS:
// BYTE strobe
// Strobe command
//-------------------------------------------------------------------------------------------------------
void halSpiStrobe(unsigned char strobe) {
// SPI0CN = 0x08; // clear all flags
NSSMD0 = 0;
while (SO_data);
// {SO_data = 0;}
SPI0DAT = strobe;
SPI_WAIT();
NSSMD0 = 1;
SO_data = 0;
}// halSpiStrobe
//-------------------------------------------------------------------------------------------------------
// void halSpiReadBurstReg(BYTE addr, BYTE *buffer, BYTE count)
//
// DESCRIPTION:
// This function reads multiple CCxxx0 register, using SPI burst access.
//
// ARGUMENTS:
// BYTE addr
// Address of the first CCxxx0 register to be accessed.
// BYTE *buffer
// Pointer to a byte array which stores the values read from a
// corresponding range of CCxxx0 registers.
// BYTE count
// Number of bytes to be written to the subsequent CCxxx0 registers.
//-------------------------------------------------------------------------------------------------------
void halSpiReadBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count) {
unsigned char i;
// SPI0CN = 0x08; // clear all flags
NSSMD0 = 0;
while (SO_data);
// {SO_data = 0;}
SPI0DAT = (addr | READ_BURST);
SPI_WAIT();
for (i = 0; i < count; i++) {
SPI0DAT = 0;
SPI_WAIT();
buffer[i] = SPI0DAT;
}
NSSMD0 = 1;
SO_data = 0;
}// halSpiReadBurstReg
unsigned char ReceivePocket_Wait(void)
{
halSpiStrobe(CCxxx0_SRX);
// Wait for GDO0 to be set -> sync received
TL1=0x00;
TH1=0xF0;
// TH1 = 0xF9;
// TL1 = 0x33;
timeoutwait=0xaa;
ET1 = 1;
TR1 = 1;
while (!GDO0)
{
if(timeoutwait==0)
return FALSE;
}
TL1=0x00;
TH1=0xF0;
//TH1 = 0xF9;
//TL1 = 0x33;
timeoutwait=0xaa;
ET1 = 1;
TR1 = 1;
// Wait for GDO0 to be cleared -> end of packet
while (GDO0)
{
if(timeoutwait==0)
return FALSE;
}
return TRUE;
}
//-------------------------------------------------------------------------------------------------------
// BOOL halRfReceivePacket(BYTE *RxTxBuffer, UINT8 length)
//
// DESCRIPTION:
// This function can be used to receive a packet of variable packet length (first byte in the packet
// must be the length byte). The packet length should not exceed the RX FIFO size.
// To use this function, GD00 must be configured to be asserted when sync word is sent and
// de-asserted at the end of the packet => halSpiWriteReg(CCxxx0_IOCFG0, 0x06);
// Also, APPEND_STATUS in the PKTCTRL1 register must be enabled.
// The function implements polling of GDO0. First it waits for GD00 to be set and then it waits
// for it to be cleared.
// After the GDO0 pin has been de-asserted, the RXBYTES register is read to make sure that there
// are bytes in the FIFO. This is because the GDO signal will indicate sync received even if the
// FIFO is flushed due to address filtering, CRC filtering, or packet length filtering.
//
// ARGUMENTS:
// BYTE *RxTxBuffer
// Pointer to the buffer where the incoming data should be stored
// UINT8 length
// Pointer to a variable containing the size of the buffer where the incoming data should be
// stored. After this function returns, that variable holds the packet length.
//
// RETURN VALUE:
// BOOL
// TRUE: CRC OK
// FALSE: CRC NOT OK (or no packet was put in the RX FIFO due to filtering)
//-------------------------------------------------------------------------------------------------------
unsigned char halRfReceivePacket(unsigned char *RxTxBuffer, unsigned char *length)
{ unsigned char value;
unsigned char status[2];
unsigned char packetLength;
unsigned char temp_HopSeq;
halSpiStrobe(CCxxx0_SIDLE);
if ((value=halSpiReadStatus(CCxxx0_RXBYTES) & BYTES_IN_RXFIFO)) {
// Read length byte
packetLength = halSpiReadReg(CCxxx0_RXFIFO);
if(packetLength ==62)
{LEVEL3=0;
LEVEL4=0;}
else
{LEVEL3=1;
LEVEL4=1;}
// Read data from RX FIFO and store in RxTxBuffer
if (packetLength <= *length) {
halSpiReadBurstReg(CCxxx0_RXFIFO, RxTxBuffer, packetLength);
*length = packetLength;
// Read the 2 appended status bytes (status[0] = RSSI, status[1] = LQI)
halSpiReadBurstReg(CCxxx0_RXFIFO, status, 2);
halSpiStrobe(CCxxx0_SIDLE);
// MSB of LQI is the CRC_OK bit
// return (status[LQI] & CRC_OK);
NewHopSeq = RxTxBuffer[2];
NexstHopSeq = RxTxBuffer[3];
temp_HopSeq = RxTxBuffer[4];
if(Reserch_hopping==0xaa)
{
Reserch_hopping = 0;
HopFre_Sequency_Nub= RxTxBuffer[5];
HopFre_Sequency_Nub++;
if(HopFre_Sequency_Nub>29)
{generateNewHopSeq (NexstHopSeq);
HopFre_Sequency_Nub = 0;}
else
generateNewHopSeq (NewHopSeq);
}
else
{
if(HopFre_Sequency_Nub>=29)
{
generateNewHopSeq (NexstHopSeq);
HopFre_Sequency_Nub = 0;
}
else
HopFre_Sequency_Nub++;
}
// Fre_Register_Setting(hopTable[HopFre_Sequency_Nub]);
return 1;
}
else
{
*length = packetLength;
//Flush RX FIFO
halSpiStrobe(CCxxx0_SFRX);
halSpiStrobe(CCxxx0_SIDLE);
if(HopFre_Sequency_Nub>29)
HopFre_Sequency_Nub = 0;
else
HopFre_Sequency_Nub++;
// Fre_Register_Setting(hopTable[HopFre_Sequency_Nub]);
return FALSE;
}
}
else
{
halSpiStrobe(CCxxx0_SIDLE);
if(HopFre_Sequency_Nub>29)
HopFre_Sequency_Nub = 0;
else
HopFre_Sequency_Nub++;
// Fre_Register_Setting(hopTable[HopFre_Sequency_Nub]);
return FALSE;
}
}// halRfReceivePacket
//-------------------------------------------------------------------------------------------------------
// void halSpiWriteBurstReg(BYTE addr, BYTE *buffer, BYTE count)
// m,.;'
// DESCRIPTION:
// This function writes to multiple CCxxx0 register, using SPI burst access.
//
// ARGUMENTS:
// BYTE addr
// Address of the first CCxxx0 register to be accessed.
// BYTE *buffer
// Array of bytes to be written into a corresponding range of
// CCxx00 registers, starting by the address specified in _addr_.
// BYTE count
// Number of bytes to be written to the subsequent CCxxx0 registers.
//-------------------------------------------------------------------------------------------------------
void halSpiWriteBurstReg(unsigned char addr, unsigned char *buffer,unsigned char count) {
unsigned char i;
// SPI0CN = 0x08; // clear all flags
NSSMD0 = 0;
while (SO_data);
SPI0DAT = addr | WRITE_BURST;
SPI_WAIT();
for (i = 0; i < count; i++) {
SPI0DAT = buffer[i];
SPI_WAIT();
}
NSSMD0 = 1;
SO_data = 0;
}// halSpiWriteBurstReg
//-----------------------------------------------------------------------------
// BYTE halSpiReadStatus(BYTE addr)
//
// DESCRIPTION:
// This function reads a CCxxx0 status register.
//
// ARGUMENTS:
// BYTE addr
// Address of the CCxxx0 status register to be accessed.
//
// RETURN VALUE:
// BYTE
// Value of the accessed CCxxx0 status register.
//-----------------------------------------------------------------------------
unsigned char halSpiReadStatus(unsigned char addr) {
unsigned char x;
// SPI0CN = 0x08; // clear all flags
NSSMD0 = 0;
while (SO_data);
// {SO_data = 0;}
SPI0DAT = (addr | READ_BURST);
SPI_WAIT();
SPI0DAT = 0;
SPI_WAIT();
x = SPI0DAT;
NSSMD0 = 1;
SO_data = 0;
return x;
}// halSpiReadStatus
void Fre_Register_Setting(unsigned char Channel_Num)
{
halSpiWriteReg(CCxxx0_CHANNR,Channel_Num);//pRfSettings->CHANNR);
}
//-------------------------------------------------------------------------------------------------------
// void afhmGenerateSeq (UINT16 seed)
//
// DESCRIPTION:
// Generate unique hop sequence based on seed value.
// 16-bit random number generator with taps at bit 13 and 14.
//-------------------------------------------------------------------------------------------------------
void generateNewHopSeq (int seed) {
unsigned char i;
int seq = seed;
unsigned char feedback = 0;
/*
for (i = 0; i < 30; i++) {
hopTable[i] = 200;
}
*/
for (i = 0; i < 30; i++) {
// XOR tap 13 and 14
if (((0x4000 & seq) && !(0x2000 & seq)) || (!(0x4000 & seq) && (0x2000 & seq)))
feedback = 1;
else
feedback = 0;
// Shift in next bit
seq = ((seq << 1) & 0xFFFE) | feedback;
if (((0x0080 & seq) && !(0x0020 & seq)) || (!(0x0080 & seq) && (0x0020 & seq)))
feedback = 1;
else
feedback = 0;
// Shift in next bit
seq = ((seq << 1) & 0xFFFE) | feedback;
hopTable[i] = seq & 0x7F;
}
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