📄 wireless_cc1100rx.c
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Audio_States Audio_LocalState; // shows whether audio signal is
Audio_States Audio_RemoteState; // "quiet" or "loud"
bit RXTX_Indicator; // shows whether RF state machine is in
// transmit or receive mode
bit OutputByteReady; // toggles to indicate whether both
// nibbles of OutputByte inside
// DPCM_Compress contain valid compressed
// data
// ReceiveFIFO Variables
unsigned char ReceiveFIFO_COUNT;
bit ReceiveFIFO_EMPTY;
bit ReceiveFIFO_OF;
bit ReceiveFIFO_UF;
bit ReceiveFIFO_FULL;
unsigned char idata ReceiveFIFO_FIRST;
unsigned char idata ReceiveFIFO_LAST;
unsigned char xdata ReceiveFIFO_FIFO[ReceiveFIFO_FIFOSIZE];
// DACTXFIFO Variables
unsigned char DACTXFIFO_COUNT;
bit DACTXFIFO_EMPTY;
bit DACTXFIFO_OF;
bit DACTXFIFO_UF;
bit DACTXFIFO_FULL;
bit DACTXFIFO_DECOMPRESS_HALT;
unsigned char idata DACTXFIFO_FIRST;
unsigned char idata DACTXFIFO_LAST;
unsigned int xdata DACTXFIFO_FIFO[DACTXFIFO_FIFOSIZE];
unsigned char xdata RxTxBuffer[65];
unsigned char length;
unsigned char code paTable[] = {0xc0};
unsigned char timeoutwait;
unsigned char HopFre_Sequency_Nub;
unsigned char NewHopSeq;
unsigned char NexstHopSeq;
unsigned char Reserch_hopping;
unsigned char Reserch_hopp_nub;
unsigned char Counter;
signed short UncompressedWord;
unsigned char temperfortest;
signed short temperfortest1;
unsigned char xdata hopTable[30];
void Fre_Register_Setting(unsigned char Channel_Num);
void generateNewHopSeq (int seed);
//-----------------------------------------------------------------------------
// MAIN Routine
//-----------------------------------------------------------------------------
main ()
{
// NewHopSeq = 0xaa; 000
// NexstHopSeq = 0xaa;
Reserch_hopp_nub = 0;
PCA0MD &= ~0x40; // disable watchdog timer
UncompressedWord = 0;
PORT_Init(); // initialize and enable the Crossbar
SYSCLK_Init(); // initialize oscillator
SPI_Init(); // init
Timer1_Init();
halWait(80); // there are 80uS space between time2 and time3
Timer3_Init(SYSCLK/DAC_UPDATERATE); // initialize timer 3 to overflow at
// DACUPDATERATE
IDAC0_Init(); // enable DAC outputs at P0.1
Variables_Init();
WaitMS(500);
POWER_UP_RESET_CCxxx0();
CCxxx0_Init(); // initalize the RF transceiver
halSpiWriteBurstReg(CCxxx0_PATABLE, paTable, sizeof(paTable));
WaitMS(200);
generateNewHopSeq (NewHopSeq);
EA = 1; // enables all interrupts
HopFre_Sequency_Nub = 0;
// Fre_Register_Setting(hopTable[HopFre_Sequency_Nub]);
Fre_Register_Setting(0);
halSpiStrobe(CCxxx0_SFRX);
WaitMS(10);
halSpiStrobe(CCxxx0_SRX);
WaitMS(100);
length=65;
ET1 = 1;
TR1 = 1;
/////////////////////////////////////////////////////////////////////////////////
while (1)
{
// FIFO_ManagementRoutine();
if(ReceivePocket_Wait())
{
if (halRfReceivePacket(RxTxBuffer, &length) )
{
// FIFO_ManagementRoutine();
for(Counter=7;Counter<62;Counter++) ///4----=59 62
{
ReceiveFIFO_Push(RxTxBuffer[Counter]);
DPCM_Decompress ();
}
DPCM_Decompress ();
}
FIFO_ManagementRoutine();
}
else
{ ET1 = 0;
TR1 = 0;
halSpiStrobe(CCxxx0_SFRX);
halSpiStrobe(CCxxx0_SIDLE);
// Fre_Register_Setting(Reserch_hopp_nub);
if(Reserch_hopp_nub>100)
Reserch_hopp_nub = 0;
else
Reserch_hopp_nub++;
Reserch_hopping = 0xaa;
WaitMS(2);
}
} // end while(1)
} // end void main()
//-----------------------------------------------------------------------------
// Initialization Functions
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
// SYSCLK_Init
//-----------------------------------------------------------------------------
//
// This routine initializes the system clock to use the internal 24.5MHz
// oscillator as its clock source. Also enables missing clock detector
// reset and enables the VDD monitor as a reset source.
//
void SYSCLK_Init (void)
{
unsigned char i;
unsigned char OSCstate;
P0&=0xF3;
OSCICN |= 0x03; // set clock to 24MHz
for(i=0;i<20;i++);
while(!(OSCXCN | 0x80));
OSCXCN = 0x67;
for(i=0;i<20;i++);//WaitMS(2);
do{
OSCstate = OSCXCN;
OSCstate &=0x80;
}while(OSCstate==80);
OSCICN |= 0x00; // set clock to 24.0 MHz
// CLKSEL = 0x01;
RSTSRC = 0x06; // enable missing clock detector
}
//-----------------------------------------------------------------------------
// PORT_Init
//-----------------------------------------------------------------------------
//
// P0.0 - VREF
// P0.1 - IDAC0 Output
// P0.2 - PSEL
// P0.3 - PCLK
// P0.4 -
// P0.5 -
// P0.6 - PDI
// P0.7 - PDO
// P1.0 - SCK (DCLK)
// P1.1 - MISO (DIO)
// P1.2 - MOSI (DIO)
// P1.3 - Audio Input
// P1.4 - Test Point
// P1.5 - LED1
// P1.6 - LED2
// P1.7 - Switch
void PORT_Init (void)
{
XBR0 |= 0x02;
XBR1 |= 0x40; // Enable crossbar, CEX0 at port pin
P0MDIN &= ~0x0D; // set P0.0 to analog input
P1MDIN &= ~0x08; // set P1.3 to analog input
// P0MDOUT = 0xf2;
// P1MDOUT = 0xf7;
P0SKIP = 0x0F; // skip ADC input P0.0,P0.1, I/O pins P0.4
P1SKIP = 0xFF; // skip all port 1 pins
}
//-----------------------------------------------------------------------------
// SPI_Init
//-----------------------------------------------------------------------------
//
// Set SPI to master, CKPHA = 0, CKPOL = 1. Set SPI to 4 wire mode, and
// enable SPI. SPI0CKR = 11, SCLK = 24.5Mhz / 12 = 1.021 MHz.
//
void SPI_Init(void)
{
SPI0CFG = 0x40; // Master disable, CKPOL = 0
SPI0CN = 0x08; // clear all flags
SPI0CKR = 0x05; // 2MHz 0x02=4MHz
SPIEN = 1; // leave SPI enable
P0MDIN |=0xF0;
P0MDOUT |= 0x70;
// P1MDIN |=0xff;
// IE |= 0x40; // enable SPI interrupts
// IP |= 0x40;
}
//-----------------------------------------------------------------------------
// IDAC0_Init
//-----------------------------------------------------------------------------
//
// Configure IDAC to update with every Timer 3 overflow, using 2.0 mA
// full-scale output current.
//
void IDAC0_Init(void)
{
IDA0CN &= ~0x70; // Clear Update Source Select Bits
IDA0CN |= 0x30; // Set DAC to update on Tmr 3 Overflows
IDA0CN |= 0x80; // Enable DAC
}
//-----------------------------------------------------------------------------
// Timer1_Init
//-----------------------------------------------------------------------------
//
// Configure Timer1
// using SYSCLK/12 as its time base. Interrupts are enabled. Timer1 controls
// the RF data pocket output time.
//
void Timer1_Init(void)
{
TMOD |= 0x10; // configure Time0 work mode;
CKCON |= 0x02; // select the clock resouce;
TF1 = 0;
TL1=0x00;
TH1=0xF0;
PT1 = 1;
}
//-----------------------------------------------------------------------------
// Timer3_Init
//-----------------------------------------------------------------------------
//
// Configure Timer3 to auto-reload at interval specified by <counts>
// using SYSCLK as its time base. Interrupts are enabled. Timer 3 controls
// the DAC output rate.
//
void Timer3_Init(unsigned int counts)
{
TMR3CN = 0x00; // resets Timer 3, sets to 16 bit mode
CKCON |= 0x40; // use system clock
TMR3RL = -counts; // Initial reload value
TMR3 = -counts; // init timer
EIE1 |= 0x80; // enable Timer 3 interrupts
TMR3CN = 0x04; // start Timer 3
}
//-----------------------------------------------------------------------------
// Variables_Init
//-----------------------------------------------------------------------------
//
void Variables_Init(void)
{
Audio_LocalState = Audio_Loud;
Audio_RemoteState = Audio_Loud;
CLEAR_FIFOS();
}
//-----------------------------------------------------------------------------
// Interrupt Service Routines
//-----------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------
// void TIMER1_ISR(void)
//
// DESCRIPTION:
// Everytime a Timer1 interrupt occurs, the duty cycle of the
// PWM is adjusted
//-------------------------------------------------------------------------------------------------------
void TIMER1_ISR(void) interrupt 3 //8ms every interruput
{
TF1 = 0;
timeoutwait = 0;
}
//-----------------------------------------------------------------------------
// Timer3_ISR
//-----------------------------------------------------------------------------
// This ISR updates the DAC output at a rate of DACUPDATERATE. It also
// fetches the most recently captured local ADC sample, attenuates the sample,
// and adds the signal to the DAC output for a loop back.
//
void TIMER3_ISR(void) interrupt 14
{
static unsigned short new_value;
// unsigned short Counter;
USHORT tempvalue;
TMR3CN &= ~0xC0; // acknowledge interrupt
//remenber
new_value = DACTXFIFO_Pull();
// only play received audio if the remote endpoint as determined
// that the audio is of audible amplitude
if(Audio_RemoteState == Audio_Loud)
{
// DAC output must be left-justified, and loaded
// low byte first
tempvalue.S = new_value;
// tempvalue.S = tempvalue.S + ADCRXFIFO_Newest()>>4;
tempvalue.S = tempvalue.S << 6;
IDA0L = tempvalue.C[1];
IDA0H = tempvalue.C[0];
}
}
//-----------------------------------------------------------------------------
// RF State Machine Functions
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// CC1100_Init
//-----------------------------------------------------------------------------
// This function will initialize the transceiver and calibrate it to
// transmit and receive on a defined frequency.
//
void CCxxx0_Init(void)
{
unsigned char i;
i = 0;
// Write register settings
halSpiWriteReg(CCxxx0_FSCTRL1, RegValue[i++]);//pRfSettings->FSCTRL1);
halSpiWriteReg(CCxxx0_FSCTRL0, RegValue[i++]);//pRfSettings->FSCTRL0);
//halSpiWriteReg(CCxxx0_FIFOTHR, 0x33);//pRfSettings->FREQ2);
halSpiWriteReg(CCxxx0_FREQ2, RegValue[i++]);//pRfSettings->FREQ2);
halSpiWriteReg(CCxxx0_FREQ1, RegValue[i++]);//pRfSettings->FREQ1);
halSpiWriteReg(CCxxx0_FREQ0, RegValue[i++]);//pRfSettings->FREQ0);
halSpiWriteReg(CCxxx0_MDMCFG4, RegValue[i++]);//pRfSettings->MDMCFG4);
halSpiWriteReg(CCxxx0_MDMCFG3, RegValue[i++]);//pRfSettings->MDMCFG3);
halSpiWriteReg(CCxxx0_MDMCFG2, RegValue[i++]);//pRfSettings->MDMCFG2);
halSpiWriteReg(CCxxx0_MDMCFG1, RegValue[i++]);//pRfSettings->MDMCFG1);
halSpiWriteReg(CCxxx0_MDMCFG0, RegValue[i++]);//pRfSettings->MDMCFG0);
halSpiWriteReg(CCxxx0_CHANNR, RegValue[i++]);//pRfSettings->CHANNR);
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