📄 wireless_cc1100rx.c
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/****************************************************************************/
/* PROJECT: Baby monitor */
/* AUTHOR: Tang Dingbo */
/* Doc: Main.c */
/* Body: c8051f330 */
/* SysFreq: 24.000 MHz */
/* DATE: 25th Aug 2007 */
/****************************************************************************/
//-----------------------------------------------------------------------------
// Wireless Voice Transmitter/Receiver by hopping frequency
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Includes
//-----------------------------------------------------------------------------
#include <c8051f330.h> // SFR declarations
#include <intrins.h> // includes the _nop_() command
//-----------------------------------------------------------------------------
// Global CONSTANTS
//-----------------------------------------------------------------------------
#define SYSCLK 24000000 // speed of internal clock
#define TransmitFIFO_FIFOSIZE 7 // sets the size of data buffers
#define ReceiveFIFO_FIFOSIZE 70 //60 63
#define DACTXFIFO_FIFOSIZE 140 //122 122
#define DAC_UPDATERATE 16000 // rate of DAC sample output 8000
// SPI related defines
#define ADDR 0x55
#define LOW 0
#define HIGH 1
// Defines
#define CRC_OK 0x80
#define RSSI 0
#define LQI 1
#define BYTES_IN_RXFIFO 0x7F
// 10-bit DPCM quantization codes
#define low_low 1
#define low_mid 2
#define low_high 4
#define middle 8
#define high_low 16
#define high_mid 32
#define high_high 64
//-------------------------------------------------------------------------------------------------------
// Definitions to support burst/single access:
#define WRITE_BURST 0x40
#define READ_SINGLE 0x80
#define READ_BURST 0xC0
//-------------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------------
// CC2500/CC1100 STROBE, CONTROL AND STATUS REGSITER
#define CCxxx0_IOCFG2 0x00 // GDO2 output pin configuration
#define CCxxx0_IOCFG1 0x01 // GDO1 output pin configuration
#define CCxxx0_IOCFG0 0x02 // GDO0 output pin configuration
#define CCxxx0_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
#define CCxxx0_SYNC1 0x04 // Sync word, high byte
#define CCxxx0_SYNC0 0x05 // Sync word, low byte
#define CCxxx0_PKTLEN 0x06 // Packet length
#define CCxxx0_PKTCTRL1 0x07 // Packet automation control
#define CCxxx0_PKTCTRL0 0x08 // Packet automation control
#define CCxxx0_ADDR 0x09 // Device address
#define CCxxx0_CHANNR 0x0A // Channel number
#define CCxxx0_FSCTRL1 0x0B // Frequency synthesizer control
#define CCxxx0_FSCTRL0 0x0C // Frequency synthesizer control
#define CCxxx0_FREQ2 0x0D // Frequency control word, high byte
#define CCxxx0_FREQ1 0x0E // Frequency control word, middle byte
#define CCxxx0_FREQ0 0x0F // Frequency control word, low byte
#define CCxxx0_MDMCFG4 0x10 // Modem configuration
#define CCxxx0_MDMCFG3 0x11 // Modem configuration
#define CCxxx0_MDMCFG2 0x12 // Modem configuration
#define CCxxx0_MDMCFG1 0x13 // Modem configuration
#define CCxxx0_MDMCFG0 0x14 // Modem configuration
#define CCxxx0_DEVIATN 0x15 // Modem deviation setting
#define CCxxx0_MCSM2 0x16 // Main Radio Control State Machine configuration
#define CCxxx0_MCSM1 0x17 // Main Radio Control State Machine configuration
#define CCxxx0_MCSM0 0x18 // Main Radio Control State Machine configuration
#define CCxxx0_FOCCFG 0x19 // Frequency Offset Compensation configuration
#define CCxxx0_BSCFG 0x1A // Bit Synchronization configuration
#define CCxxx0_AGCCTRL2 0x1B // AGC control
#define CCxxx0_AGCCTRL1 0x1C // AGC control
#define CCxxx0_AGCCTRL0 0x1D // AGC control
#define CCxxx0_WOREVT1 0x1E // High byte Event 0 timeout
#define CCxxx0_WOREVT0 0x1F // Low byte Event 0 timeout
#define CCxxx0_WORCTRL 0x20 // Wake On Radio control
#define CCxxx0_FREND1 0x21 // Front end RX configuration
#define CCxxx0_FREND0 0x22 // Front end TX configuration
#define CCxxx0_FSCAL3 0x23 // Frequency synthesizer calibration
#define CCxxx0_FSCAL2 0x24 // Frequency synthesizer calibration
#define CCxxx0_FSCAL1 0x25 // Frequency synthesizer calibration
#define CCxxx0_FSCAL0 0x26 // Frequency synthesizer calibration
#define CCxxx0_RCCTRL1 0x27 // RC oscillator configuration
#define CCxxx0_RCCTRL0 0x28 // RC oscillator configuration
#define CCxxx0_FSTEST 0x29 // Frequency synthesizer calibration control
#define CCxxx0_PTEST 0x2A // Production test
#define CCxxx0_AGCTEST 0x2B // AGC test
#define CCxxx0_TEST2 0x2C // Various test settings
#define CCxxx0_TEST1 0x2D // Various test settings
#define CCxxx0_TEST0 0x2E // Various test settings
// Strobe commands
#define CCxxx0_SRES 0x30 // Reset chip.
#define CCxxx0_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1).
// If in RX/TX: Go to a wait state where only the synthesizer is
// running (for quick RX / TX turnaround).
#define CCxxx0_SXOFF 0x32 // Turn off crystal oscillator.
#define CCxxx0_SCAL 0x33 // Calibrate frequency synthesizer and turn it off
// (enables quick start).
#define CCxxx0_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and
// MCSM0.FS_AUTOCAL=1.
#define CCxxx0_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if
// MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled:
// Only go to TX if channel is clear.
#define CCxxx0_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit
// Wake-On-Radio mode if applicable.
#define CCxxx0_SAFC 0x37 // Perform AFC adjustment of the frequency synthesizer
#define CCxxx0_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio)
#define CCxxx0_SPWD 0x39 // Enter power down mode when CSn goes high.
#define CCxxx0_SFRX 0x3A // Flush the RX FIFO buffer.
#define CCxxx0_SFTX 0x3B // Flush the TX FIFO buffer.
#define CCxxx0_SWORRST 0x3C // Reset real time clock.
#define CCxxx0_SNOP 0x3D // No operation. May be used to pad strobe commands to two
// bytes for simpler software.
#define CCxxx0_PARTNUM 0x30
#define CCxxx0_VERSION 0x31
#define CCxxx0_FREQEST 0x32
#define CCxxx0_LQI 0x33
#define CCxxx0_RSSI 0x34
#define CCxxx0_MARCSTATE 0x35
#define CCxxx0_WORTIME1 0x36
#define CCxxx0_WORTIME0 0x37
#define CCxxx0_PKTSTATUS 0x38
#define CCxxx0_VCO_VC_DAC 0x39
#define CCxxx0_TXBYTES 0x3A
#define CCxxx0_RXBYTES 0x3B
#define CCxxx0_PATABLE 0x3E
#define CCxxx0_TXFIFO 0x3F
#define CCxxx0_RXFIFO 0x3F
//-----------------------------------------------------------------------------
// 16-bit SFR Definitions for 'F33x
//-----------------------------------------------------------------------------
sfr16 DP = 0x82; // data pointer
sfr16 TMR3RL = 0x92; // Timer3 reload value
sfr16 TMR3 = 0x94; // Timer3 counter
sfr16 IDA0 = 0x96; // IDAC0 data
sfr16 ADC0 = 0xbd; // ADC0 data
sfr16 ADC0GT = 0xc3; // ADC0 Greater-Than
sfr16 ADC0LT = 0xc5; // ADC0 Less-Than
sfr16 TMR2RL = 0xca; // Timer2 reload value
sfr16 TMR2 = 0xcc; // Timer2 counter
sfr16 PCA0CP1 = 0xe9; // PCA0 Module 1 Capture/Compare
sfr16 PCA0CP2 = 0xeb; // PCA0 Module 2 Capture/Compare
sfr16 PCA0 = 0xf9; // PCA0 counter
sfr16 PCA0CP0 = 0xfb; // PCA0 Module 0 Capture/Compare
//-----------------------------------------------------------------------------
// Function PROTOTYPES
//-----------------------------------------------------------------------------
void SYSCLK_Init (void); // initialize system clock to 24.5 MHz
void PORT_Init (void); // initialize crossbar
void Timer1_Init(void); // interrupts enabled
void Timer3_Init(unsigned int); // sets DAC output rate
void IDAC0_Init(void); // enables IDAC output on P0.1
void SPI_Init(void); // enable 3-wire Slave SPI for RF trans.
// DATA interface
void Variables_Init(void); // set global variables to reset values
void Timer3_ISR (void); // updates the DAC
void TIMER1_ISR(void);
// FIFO Routines
unsigned char ReceiveFIFO_Pull(); // pulls RXed compressed sample
unsigned short DACTXFIFO_Pull(); // pulls decompressed sample
void ReceiveFIFO_Push(unsigned char); // pushes RXed compressed sample
void DACTXFIFO_Push(unsigned short); // pushes decompressed sample
void CLEAR_FIFOS(void); // resets all FIFOs to default values
// DPCM Compression Algorithms
void DPCM_Decompress(void); // Compresses an ADC sample
//the mcu communicte with cc1100 by spi
//
void CCxxx0_Init(void);
unsigned char halSpiReadStatus(unsigned char addr);
void halSpiStrobe(unsigned char strobe);
void SPI_WAIT(void);
void POWER_UP_RESET_CCxxx0(void);
void halWait(int timeout);
void WaitMS(unsigned int);
void FIFO_ManagementRoutine(void); // encapsulates all foreground function
// calls concerning buffers, and
// all checks and tests on buffer
// sizes
void createDataPacket(unsigned char Counter_Pocket);
unsigned char halSpiReadReg(unsigned char addr);
void halSpiWriteReg(unsigned char addr, unsigned char value);
void halSpiReadBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count);
void halSpiWriteBurstReg(unsigned char addr, unsigned char *buffer,unsigned char count);
unsigned char ReceivePocket_Wait(void);
unsigned char halRfReceivePacket(unsigned char *RxTxBuffer, unsigned char *length);
//-----------------------------------------------------------------------------
// User-Defined Types
//-----------------------------------------------------------------------------
typedef union USHORT { // access a short variable as two
unsigned short S; // 8-bit integer values
unsigned char C[2];
} USHORT;
enum Logic{ FALSE, TRUE};
typedef enum Audio_States{
Audio_Quiet = 0x10,
// state indicates that audio is below the audible threshold
Audio_Loud = 0x30,
// audio is above audible threshold
Audio_ChannelShutdown = 0x40
// special state transmitted after both Endpoints' Audio States have
// been set to
} Audio_States;
//-----------------------------------------------------------------------------
// Global Variables
//-----------------------------------------------------------------------------
// Chipcon
// Product = CC1100
// Chip version = F
// Crystal accuracy = 40 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 541.666667 kHz
// Phase = 0
// Datarate = 249.938965 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 914.999969 MHz
// Channel spacing = 199.951172 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (2) Enable infinite length packets.
// Packetlength = 255
// Preamble count = (2) 4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (11) Serial Clock
unsigned char code RegValue[] = {
0x0A, // FSCTRL1 Frequency synthesizer control.
0x00, // FSCTRL0 Frequency synthesizer control.
0x23, // FREQ2 Frequency control word, high byte.
0x31, // FREQ1 Frequency control word, middle byte.
0x3B, // FREQ0 Frequency control word, low byte.
0x5D, // MDMCFG4 Modem configuration. 2D
0x3B, // MDMCFG3 Modem configuration.
0x73, // MDMCFG2 Modem configuration.
0x22, // MDMCFG1 Modem configuration.
0xF8, // MDMCFG0 Modem configuration.
0x00, // CHANNR Channel number.
0x00, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0xB6, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end RX configuration.
0x18, // MCSM0 Main Radio Control State Machine configuration. 18
0x1D, // FOCCFG Frequency Offset Compensation Configuration.
0x1C, // BSCFG Bit synchronization Configuration.
0xC7, // AGCCTRL2 AGC control.
0x00, // AGCCTRL1 AGC control.
0xB2, // AGCCTRL0 AGC control.
0xEA, // FSCAL3 Frequency synthesizer calibration.
0x2A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x1F, // FSCAL0 Frequency synthesizer calibration.
0x59, // FSTEST Frequency synthesizer calibration.
0x88, // TEST2 Various test settings.
0x31, // TEST1 Various test settings.
0x09, // TEST0 Various test settings.
0x06, // IOCFG2 GDO2 output pin configuration.
0x0B, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.
0x04, // PKTCTRL1 Packet automation control.
0x06, // PKTCTRL0 Packet automation control.
0x00, // ADDR Device address.
0xFF // PKTLEN Packet length.
};
/*
unsigned char code RegValue[] = {
0x08, // FSCTRL1 Frequency synthesizer control.
0x00, // FSCTRL0 Frequency synthesizer control.
0x22, // FREQ2 Frequency control word, high byte. 23
0xCE, // FREQ1 Frequency control word, middle byte. 31
0xC4, // FREQ0 Frequency control word, low byte. 3B
0x7B, // MDMCFG4 Modem configuration. 2D
0x83, // MDMCFG3 Modem configuration.
0x03, // MDMCFG2 Modem configuration.
0x22, // MDMCFG1 Modem configuration.
0xF8, // MDMCFG0 Modem configuration.
0x00, // CHANNR Channel number.
0x42, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0xB6, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end RX configuration.
0x18, // MCSM0 Main Radio Control State Machine configuration. 18
0x1D, // FOCCFG Frequency Offset Compensation Configuration.
0x1C, // BSCFG Bit synchronization Configuration.
0xC7, // AGCCTRL2 AGC control.
0x00, // AGCCTRL1 AGC control.
0xB2, // AGCCTRL0 AGC control.
0xEA, // FSCAL3 Frequency synthesizer calibration.
0x2A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x1F, // FSCAL0 Frequency synthesizer calibration.
0x59, // FSTEST Frequency synthesizer calibration.
0x81, // TEST2 Various test settings.
0x35, // TEST1 Various test settings.
0x09, // TEST0 Various test settings.
0x06, // IOCFG2 GDO2 output pin configuration.
0x0B, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.
0x04, // PKTCTRL1 Packet automation control. 0x04
0x06, // PKTCTRL0 Packet automation control.
0x55, // ADDR Device address.
0xFF // PKTLEN Packet length.
};
*/
// the mapping from DPCM quantization values to dpcm codes (array index)
short code Q_VALUES[16] = {0,
-high_high,
-high_mid,
-high_low,
-middle,
-low_high,
-low_mid,
-low_low,
0,
low_low,
low_mid,
low_high,
middle,
high_low,
high_mid,
high_high};
// CC1100 Interface Bits
sbit SCLK = P0^4; //SPI interface
sbit SO_data = P0^5;
sbit SI_data = P0^6;
sbit CSn = P0^7; //SPI interface
sbit GDO0 = P1^0;
sbit LEVEL1 = P1^2;
sbit LEVEL2 = P1^7;
sbit LEVEL3 = P1^6;
sbit LEVEL4 = P1^5;
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