📄 wireless_cc1100rx.lst
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481 1
482 1 WaitMS(200);
483 1
484 1 generateNewHopSeq (NewHopSeq);
C51 COMPILER V8.05a WIRELESS_CC1100RX 11/07/2007 15:16:42 PAGE 9
485 1 EA = 1; // enables all interrupts
486 1
487 1 HopFre_Sequency_Nub = 0;
488 1
489 1 // Fre_Register_Setting(hopTable[HopFre_Sequency_Nub]);
490 1 Fre_Register_Setting(0);
491 1
492 1 halSpiStrobe(CCxxx0_SFRX);
493 1
494 1 WaitMS(10);
495 1 halSpiStrobe(CCxxx0_SRX);
496 1 WaitMS(100);
497 1 length=65;
498 1 ET1 = 1;
499 1 TR1 = 1;
500 1 /////////////////////////////////////////////////////////////////////////////////
501 1 while (1)
502 1 {
503 2 // FIFO_ManagementRoutine();
504 2 if(ReceivePocket_Wait())
505 2 {
506 3 if (halRfReceivePacket(RxTxBuffer, &length) )
507 3 {
508 4 // FIFO_ManagementRoutine();
509 4 for(Counter=7;Counter<62;Counter++) ///4----=59 62
510 4 {
511 5 ReceiveFIFO_Push(RxTxBuffer[Counter]);
512 5 DPCM_Decompress ();
513 5 }
514 4 DPCM_Decompress ();
515 4 }
516 3 FIFO_ManagementRoutine();
517 3
518 3 }
519 2 else
520 2 { ET1 = 0;
521 3 TR1 = 0;
522 3 halSpiStrobe(CCxxx0_SFRX);
523 3 halSpiStrobe(CCxxx0_SIDLE);
524 3 // Fre_Register_Setting(Reserch_hopp_nub);
525 3 if(Reserch_hopp_nub>100)
526 3 Reserch_hopp_nub = 0;
527 3 else
528 3 Reserch_hopp_nub++;
529 3 Reserch_hopping = 0xaa;
530 3 WaitMS(2);
531 3 }
532 2
533 2
534 2 } // end while(1)
535 1
536 1 } // end void main()
537
538
539 //-----------------------------------------------------------------------------
540 // Initialization Functions
541 //-----------------------------------------------------------------------------
542 //
543
544 //-----------------------------------------------------------------------------
545 // SYSCLK_Init
546 //-----------------------------------------------------------------------------
C51 COMPILER V8.05a WIRELESS_CC1100RX 11/07/2007 15:16:42 PAGE 10
547 //
548 // This routine initializes the system clock to use the internal 24.5MHz
549 // oscillator as its clock source. Also enables missing clock detector
550 // reset and enables the VDD monitor as a reset source.
551 //
552 void SYSCLK_Init (void)
553 {
554 1 unsigned char i;
555 1 unsigned char OSCstate;
556 1 P0&=0xF3;
557 1 OSCICN |= 0x03; // set clock to 24MHz
558 1 for(i=0;i<20;i++);
559 1 while(!(OSCXCN | 0x80));
560 1 OSCXCN = 0x67;
561 1 for(i=0;i<20;i++);//WaitMS(2);
562 1 do{
563 2 OSCstate = OSCXCN;
564 2 OSCstate &=0x80;
565 2
566 2 }while(OSCstate==80);
567 1 OSCICN |= 0x00; // set clock to 24.0 MHz
568 1
569 1 // CLKSEL = 0x01;
570 1
571 1
572 1 RSTSRC = 0x06; // enable missing clock detector
573 1 }
574
575 //-----------------------------------------------------------------------------
576 // PORT_Init
577 //-----------------------------------------------------------------------------
578 //
579 // P0.0 - VREF
580 // P0.1 - IDAC0 Output
581 // P0.2 - PSEL
582 // P0.3 - PCLK
583 // P0.4 -
584 // P0.5 -
585 // P0.6 - PDI
586 // P0.7 - PDO
587 // P1.0 - SCK (DCLK)
588 // P1.1 - MISO (DIO)
589 // P1.2 - MOSI (DIO)
590 // P1.3 - Audio Input
591 // P1.4 - Test Point
592 // P1.5 - LED1
593 // P1.6 - LED2
594 // P1.7 - Switch
595
596 void PORT_Init (void)
597 {
598 1 XBR0 |= 0x02;
599 1 XBR1 |= 0x40; // Enable crossbar, CEX0 at port pin
600 1
601 1 P0MDIN &= ~0x0D; // set P0.0 to analog input
602 1 P1MDIN &= ~0x08; // set P1.3 to analog input
603 1
604 1 // P0MDOUT = 0xf2;
605 1 // P1MDOUT = 0xf7;
606 1
607 1 P0SKIP = 0x0F; // skip ADC input P0.0,P0.1, I/O pins P0.4
608 1 P1SKIP = 0xFF; // skip all port 1 pins
C51 COMPILER V8.05a WIRELESS_CC1100RX 11/07/2007 15:16:42 PAGE 11
609 1
610 1 }
611
612 //-----------------------------------------------------------------------------
613 // SPI_Init
614 //-----------------------------------------------------------------------------
615 //
616 // Set SPI to master, CKPHA = 0, CKPOL = 1. Set SPI to 4 wire mode, and
617 // enable SPI. SPI0CKR = 11, SCLK = 24.5Mhz / 12 = 1.021 MHz.
618 //
619 void SPI_Init(void)
620 {
621 1 SPI0CFG = 0x40; // Master disable, CKPOL = 0
622 1 SPI0CN = 0x08; // clear all flags
623 1 SPI0CKR = 0x05; // 2MHz 0x02=4MHz
624 1 SPIEN = 1; // leave SPI enable
625 1 P0MDIN |=0xF0;
626 1 P0MDOUT |= 0x70;
627 1 // P1MDIN |=0xff;
628 1
629 1 // IE |= 0x40; // enable SPI interrupts
630 1 // IP |= 0x40;
631 1
632 1 }
633
634
635 //-----------------------------------------------------------------------------
636 // IDAC0_Init
637 //-----------------------------------------------------------------------------
638 //
639 // Configure IDAC to update with every Timer 3 overflow, using 2.0 mA
640 // full-scale output current.
641 //
642
643 void IDAC0_Init(void)
644 {
645 1 IDA0CN &= ~0x70; // Clear Update Source Select Bits
646 1 IDA0CN |= 0x30; // Set DAC to update on Tmr 3 Overflows
647 1 IDA0CN |= 0x80; // Enable DAC
648 1
649 1 }
650
651 //-----------------------------------------------------------------------------
652 // Timer1_Init
653 //-----------------------------------------------------------------------------
654 //
655 // Configure Timer1
656 // using SYSCLK/12 as its time base. Interrupts are enabled. Timer1 controls
657 // the RF data pocket output time.
658 //
659 void Timer1_Init(void)
660 {
661 1 TMOD |= 0x10; // configure Time0 work mode;
662 1
663 1 CKCON |= 0x02; // select the clock resouce;
664 1
665 1
666 1 TF1 = 0;
667 1 TL1=0x00;
668 1 TH1=0xF0;
669 1
670 1 PT1 = 1;
C51 COMPILER V8.05a WIRELESS_CC1100RX 11/07/2007 15:16:42 PAGE 12
671 1 }
672 //-----------------------------------------------------------------------------
673 // Timer3_Init
674 //-----------------------------------------------------------------------------
675 //
676 // Configure Timer3 to auto-reload at interval specified by <counts>
677 // using SYSCLK as its time base. Interrupts are enabled. Timer 3 controls
678 // the DAC output rate.
679 //
680 void Timer3_Init(unsigned int counts)
681 {
682 1 TMR3CN = 0x00; // resets Timer 3, sets to 16 bit mode
683 1 CKCON |= 0x40; // use system clock
684 1 TMR3RL = -counts; // Initial reload value
685 1
686 1 TMR3 = -counts; // init timer
687 1 EIE1 |= 0x80; // enable Timer 3 interrupts
688 1 TMR3CN = 0x04; // start Timer 3
689 1 }
690
691
692 //-----------------------------------------------------------------------------
693 // Variables_Init
694 //-----------------------------------------------------------------------------
695 //
696 void Variables_Init(void)
697 {
698 1 Audio_LocalState = Audio_Loud;
699 1 Audio_RemoteState = Audio_Loud;
700 1
701 1 CLEAR_FIFOS();
702 1 }
703
704
705 //-----------------------------------------------------------------------------
706 // Interrupt Service Routines
707 //-----------------------------------------------------------------------------
708 //-------------------------------------------------------------------------------------------------------
709 // void TIMER1_ISR(void)
710 //
711 // DESCRIPTION:
712 // Everytime a Timer1 interrupt occurs, the duty cycle of the
713 // PWM is adjusted
714 //-------------------------------------------------------------------------------------------------------
715 void TIMER1_ISR(void) interrupt 3 //8ms every interruput
716 {
717 1 TF1 = 0;
718 1 timeoutwait = 0;
719 1 }
720
721
722 //-----------------------------------------------------------------------------
723 // Timer3_ISR
724 //-----------------------------------------------------------------------------
725 // This ISR updates the DAC output at a rate of DACUPDATERATE. It also
726 // fetches the most recently captured local ADC sample, attenuates the sample,
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