📄 wireless_cc1100rx.lst
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239 typedef enum Audio_States{
240 Audio_Quiet = 0x10,
C51 COMPILER V8.05a WIRELESS_CC1100RX 11/07/2007 15:16:42 PAGE 5
241 // state indicates that audio is below the audible threshold
242
243 Audio_Loud = 0x30,
244 // audio is above audible threshold
245
246 Audio_ChannelShutdown = 0x40
247 // special state transmitted after both Endpoints' Audio States have
248 // been set to
249
250 } Audio_States;
251
252 //-----------------------------------------------------------------------------
253 // Global Variables
254 //-----------------------------------------------------------------------------
255 // Chipcon
256 // Product = CC1100
257 // Chip version = F
258 // Crystal accuracy = 40 ppm
259 // X-tal frequency = 26 MHz
260 // RF output power = 0 dBm
261 // RX filterbandwidth = 541.666667 kHz
262 // Phase = 0
263 // Datarate = 249.938965 kbps
264 // Modulation = (7) MSK
265 // Manchester enable = (0) Manchester disabled
266 // RF Frequency = 914.999969 MHz
267 // Channel spacing = 199.951172 kHz
268 // Channel number = 0
269 // Optimization = Sensitivity
270 // Sync mode = (3) 30/32 sync word bits detected
271 // Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
272 // CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
273 // Forward Error Correction = (0) FEC disabled
274 // Length configuration = (2) Enable infinite length packets.
275 // Packetlength = 255
276 // Preamble count = (2) 4 bytes
277 // Append status = 1
278 // Address check = (0) No address check
279 // FIFO autoflush = 0
280 // Device address = 0
281 // GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end
- of the packet
282 // GDO2 signal selection = (11) Serial Clock
283
284 unsigned char code RegValue[] = {
285 0x0A, // FSCTRL1 Frequency synthesizer control.
286 0x00, // FSCTRL0 Frequency synthesizer control.
287 0x23, // FREQ2 Frequency control word, high byte.
288 0x31, // FREQ1 Frequency control word, middle byte.
289 0x3B, // FREQ0 Frequency control word, low byte.
290 0x5D, // MDMCFG4 Modem configuration. 2D
291 0x3B, // MDMCFG3 Modem configuration.
292 0x73, // MDMCFG2 Modem configuration.
293 0x22, // MDMCFG1 Modem configuration.
294 0xF8, // MDMCFG0 Modem configuration.
295 0x00, // CHANNR Channel number.
296 0x00, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
297 0xB6, // FREND1 Front end RX configuration.
298 0x10, // FREND0 Front end RX configuration.
299 0x18, // MCSM0 Main Radio Control State Machine configuration. 18
300 0x1D, // FOCCFG Frequency Offset Compensation Configuration.
301 0x1C, // BSCFG Bit synchronization Configuration.
C51 COMPILER V8.05a WIRELESS_CC1100RX 11/07/2007 15:16:42 PAGE 6
302 0xC7, // AGCCTRL2 AGC control.
303 0x00, // AGCCTRL1 AGC control.
304 0xB2, // AGCCTRL0 AGC control.
305 0xEA, // FSCAL3 Frequency synthesizer calibration.
306 0x2A, // FSCAL2 Frequency synthesizer calibration.
307 0x00, // FSCAL1 Frequency synthesizer calibration.
308 0x1F, // FSCAL0 Frequency synthesizer calibration.
309 0x59, // FSTEST Frequency synthesizer calibration.
310 0x88, // TEST2 Various test settings.
311 0x31, // TEST1 Various test settings.
312 0x09, // TEST0 Various test settings.
313 0x06, // IOCFG2 GDO2 output pin configuration.
314 0x0B, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed p
-seudo register explanation.
315 0x04, // PKTCTRL1 Packet automation control.
316 0x06, // PKTCTRL0 Packet automation control.
317 0x00, // ADDR Device address.
318 0xFF // PKTLEN Packet length.
319
320 };
321
322 /*
323 unsigned char code RegValue[] = {
324 0x08, // FSCTRL1 Frequency synthesizer control.
325 0x00, // FSCTRL0 Frequency synthesizer control.
326 0x22, // FREQ2 Frequency control word, high byte. 23
327 0xCE, // FREQ1 Frequency control word, middle byte. 31
328 0xC4, // FREQ0 Frequency control word, low byte. 3B
329 0x7B, // MDMCFG4 Modem configuration. 2D
330 0x83, // MDMCFG3 Modem configuration.
331 0x03, // MDMCFG2 Modem configuration.
332 0x22, // MDMCFG1 Modem configuration.
333 0xF8, // MDMCFG0 Modem configuration.
334 0x00, // CHANNR Channel number.
335 0x42, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
336 0xB6, // FREND1 Front end RX configuration.
337 0x10, // FREND0 Front end RX configuration.
338 0x18, // MCSM0 Main Radio Control State Machine configuration. 18
339 0x1D, // FOCCFG Frequency Offset Compensation Configuration.
340 0x1C, // BSCFG Bit synchronization Configuration.
341 0xC7, // AGCCTRL2 AGC control.
342 0x00, // AGCCTRL1 AGC control.
343 0xB2, // AGCCTRL0 AGC control.
344 0xEA, // FSCAL3 Frequency synthesizer calibration.
345 0x2A, // FSCAL2 Frequency synthesizer calibration.
346 0x00, // FSCAL1 Frequency synthesizer calibration.
347 0x1F, // FSCAL0 Frequency synthesizer calibration.
348 0x59, // FSTEST Frequency synthesizer calibration.
349 0x81, // TEST2 Various test settings.
350 0x35, // TEST1 Various test settings.
351 0x09, // TEST0 Various test settings.
352 0x06, // IOCFG2 GDO2 output pin configuration.
353 0x0B, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed p
-seudo register explanation.
354 0x04, // PKTCTRL1 Packet automation control. 0x04
355 0x06, // PKTCTRL0 Packet automation control.
356 0x55, // ADDR Device address.
357 0xFF // PKTLEN Packet length.
358
359 };
360
361 */
C51 COMPILER V8.05a WIRELESS_CC1100RX 11/07/2007 15:16:42 PAGE 7
362 // the mapping from DPCM quantization values to dpcm codes (array index)
363 short code Q_VALUES[16] = {0,
364 -high_high,
365 -high_mid,
366 -high_low,
367 -middle,
368 -low_high,
369 -low_mid,
370 -low_low,
371 0,
372 low_low,
373 low_mid,
374 low_high,
375 middle,
376 high_low,
377 high_mid,
378 high_high};
379
380 // CC1100 Interface Bits
381 sbit SCLK = P0^4; //SPI interface
382 sbit SO_data = P0^5;
383 sbit SI_data = P0^6;
384 sbit CSn = P0^7; //SPI interface
385 sbit GDO0 = P1^0;
386
387
388 sbit LEVEL1 = P1^2;
389 sbit LEVEL2 = P1^7;
390 sbit LEVEL3 = P1^6;
391 sbit LEVEL4 = P1^5;
392
393 Audio_States Audio_LocalState; // shows whether audio signal is
394 Audio_States Audio_RemoteState; // "quiet" or "loud"
395
396 bit RXTX_Indicator; // shows whether RF state machine is in
397 // transmit or receive mode
398
399 bit OutputByteReady; // toggles to indicate whether both
400 // nibbles of OutputByte inside
401 // DPCM_Compress contain valid compressed
402 // data
403
404 // ReceiveFIFO Variables
405 unsigned char ReceiveFIFO_COUNT;
406 bit ReceiveFIFO_EMPTY;
407 bit ReceiveFIFO_OF;
408 bit ReceiveFIFO_UF;
409 bit ReceiveFIFO_FULL;
410 unsigned char idata ReceiveFIFO_FIRST;
411 unsigned char idata ReceiveFIFO_LAST;
412 unsigned char xdata ReceiveFIFO_FIFO[ReceiveFIFO_FIFOSIZE];
413
414 // DACTXFIFO Variables
415 unsigned char DACTXFIFO_COUNT;
416 bit DACTXFIFO_EMPTY;
417 bit DACTXFIFO_OF;
418 bit DACTXFIFO_UF;
419 bit DACTXFIFO_FULL;
420 bit DACTXFIFO_DECOMPRESS_HALT;
421 unsigned char idata DACTXFIFO_FIRST;
422 unsigned char idata DACTXFIFO_LAST;
423 unsigned int xdata DACTXFIFO_FIFO[DACTXFIFO_FIFOSIZE];
C51 COMPILER V8.05a WIRELESS_CC1100RX 11/07/2007 15:16:42 PAGE 8
424
425
426 unsigned char xdata RxTxBuffer[65];
427 unsigned char length;
428 unsigned char code paTable[] = {0xc0};
429
430 unsigned char timeoutwait;
431 unsigned char HopFre_Sequency_Nub;
432 unsigned char NewHopSeq;
433 unsigned char NexstHopSeq;
434 unsigned char Reserch_hopping;
435 unsigned char Reserch_hopp_nub;
436 unsigned char Counter;
437
438 signed short UncompressedWord;
439
440 unsigned char temperfortest;
441 signed short temperfortest1;
442
443 unsigned char xdata hopTable[30];
444
445
446 void Fre_Register_Setting(unsigned char Channel_Num);
447 void generateNewHopSeq (int seed);
448 //-----------------------------------------------------------------------------
449 // MAIN Routine
450 //-----------------------------------------------------------------------------
451 main ()
452 {
453 1 // NewHopSeq = 0xaa;
- 000
454 1 // NexstHopSeq = 0xaa;
455 1 Reserch_hopp_nub = 0;
456 1 PCA0MD &= ~0x40; // disable watchdog timer
457 1
458 1 UncompressedWord = 0;
459 1
460 1 PORT_Init(); // initialize and enable the Crossbar
461 1
462 1 SYSCLK_Init(); // initialize oscillator
463 1 SPI_Init(); // init
464 1 Timer1_Init();
465 1 halWait(80); // there are 80uS space between time2 and time3
466 1
467 1
468 1 Timer3_Init(SYSCLK/DAC_UPDATERATE); // initialize timer 3 to overflow at
469 1 // DACUPDATERATE
470 1 IDAC0_Init(); // enable DAC outputs at P0.1
471 1
472 1 Variables_Init();
473 1
474 1 WaitMS(500);
475 1
476 1 POWER_UP_RESET_CCxxx0();
477 1
478 1 CCxxx0_Init(); // initalize the RF transceiver
479 1
480 1 halSpiWriteBurstReg(CCxxx0_PATABLE, paTable, sizeof(paTable));
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