📄 wireless_cc1100rx.lst
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C51 COMPILER V8.05a WIRELESS_CC1100RX 11/07/2007 15:16:42 PAGE 1
C51 COMPILER V8.05a, COMPILATION OF MODULE WIRELESS_CC1100RX
OBJECT MODULE PLACED IN wireless_cc1100Rx.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE wireless_cc1100Rx.c BROWSE DEBUG OBJECTEXTEND
line level source
1 /****************************************************************************/
2 /* PROJECT: Baby monitor */
3 /* AUTHOR: Tang Dingbo */
4 /* Doc: Main.c */
5 /* Body: c8051f330 */
6 /* SysFreq: 24.000 MHz */
7 /* DATE: 25th Aug 2007 */
8 /****************************************************************************/
9 //-----------------------------------------------------------------------------
10 // Wireless Voice Transmitter/Receiver by hopping frequency
11 //-----------------------------------------------------------------------------
12 //-----------------------------------------------------------------------------
13 // Includes
14 //-----------------------------------------------------------------------------
15 #include <c8051f330.h> // SFR declarations
16 #include <intrins.h> // includes the _nop_() command
17
18 //-----------------------------------------------------------------------------
19 // Global CONSTANTS
20 //-----------------------------------------------------------------------------
21
22
23 #define SYSCLK 24000000 // speed of internal clock
24 #define TransmitFIFO_FIFOSIZE 7 // sets the size of data buffers
25 #define ReceiveFIFO_FIFOSIZE 70 //60 63
26 #define DACTXFIFO_FIFOSIZE 140 //122 122
27
28 #define DAC_UPDATERATE 16000 // rate of DAC sample output 8000
29
30
31
32 // SPI related defines
33 #define ADDR 0x55
34 #define LOW 0
35 #define HIGH 1
36
37 // Defines
38 #define CRC_OK 0x80
39 #define RSSI 0
40 #define LQI 1
41 #define BYTES_IN_RXFIFO 0x7F
42
43 // 10-bit DPCM quantization codes
44 #define low_low 1
45 #define low_mid 2
46 #define low_high 4
47 #define middle 8
48 #define high_low 16
49 #define high_mid 32
50 #define high_high 64
51
52 //-------------------------------------------------------------------------------------------------------
53 // Definitions to support burst/single access:
54 #define WRITE_BURST 0x40
55 #define READ_SINGLE 0x80
C51 COMPILER V8.05a WIRELESS_CC1100RX 11/07/2007 15:16:42 PAGE 2
56 #define READ_BURST 0xC0
57 //-------------------------------------------------------------------------------------------------------
58
59 //------------------------------------------------------------------------------------------------------
60 // CC2500/CC1100 STROBE, CONTROL AND STATUS REGSITER
61 #define CCxxx0_IOCFG2 0x00 // GDO2 output pin configuration
62 #define CCxxx0_IOCFG1 0x01 // GDO1 output pin configuration
63 #define CCxxx0_IOCFG0 0x02 // GDO0 output pin configuration
64 #define CCxxx0_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
65 #define CCxxx0_SYNC1 0x04 // Sync word, high byte
66 #define CCxxx0_SYNC0 0x05 // Sync word, low byte
67 #define CCxxx0_PKTLEN 0x06 // Packet length
68 #define CCxxx0_PKTCTRL1 0x07 // Packet automation control
69 #define CCxxx0_PKTCTRL0 0x08 // Packet automation control
70 #define CCxxx0_ADDR 0x09 // Device address
71 #define CCxxx0_CHANNR 0x0A // Channel number
72 #define CCxxx0_FSCTRL1 0x0B // Frequency synthesizer control
73 #define CCxxx0_FSCTRL0 0x0C // Frequency synthesizer control
74 #define CCxxx0_FREQ2 0x0D // Frequency control word, high byte
75 #define CCxxx0_FREQ1 0x0E // Frequency control word, middle byte
76 #define CCxxx0_FREQ0 0x0F // Frequency control word, low byte
77 #define CCxxx0_MDMCFG4 0x10 // Modem configuration
78 #define CCxxx0_MDMCFG3 0x11 // Modem configuration
79 #define CCxxx0_MDMCFG2 0x12 // Modem configuration
80 #define CCxxx0_MDMCFG1 0x13 // Modem configuration
81 #define CCxxx0_MDMCFG0 0x14 // Modem configuration
82 #define CCxxx0_DEVIATN 0x15 // Modem deviation setting
83 #define CCxxx0_MCSM2 0x16 // Main Radio Control State Machine configuration
84 #define CCxxx0_MCSM1 0x17 // Main Radio Control State Machine configuration
85 #define CCxxx0_MCSM0 0x18 // Main Radio Control State Machine configuration
86 #define CCxxx0_FOCCFG 0x19 // Frequency Offset Compensation configuration
87 #define CCxxx0_BSCFG 0x1A // Bit Synchronization configuration
88 #define CCxxx0_AGCCTRL2 0x1B // AGC control
89 #define CCxxx0_AGCCTRL1 0x1C // AGC control
90 #define CCxxx0_AGCCTRL0 0x1D // AGC control
91 #define CCxxx0_WOREVT1 0x1E // High byte Event 0 timeout
92 #define CCxxx0_WOREVT0 0x1F // Low byte Event 0 timeout
93 #define CCxxx0_WORCTRL 0x20 // Wake On Radio control
94 #define CCxxx0_FREND1 0x21 // Front end RX configuration
95 #define CCxxx0_FREND0 0x22 // Front end TX configuration
96 #define CCxxx0_FSCAL3 0x23 // Frequency synthesizer calibration
97 #define CCxxx0_FSCAL2 0x24 // Frequency synthesizer calibration
98 #define CCxxx0_FSCAL1 0x25 // Frequency synthesizer calibration
99 #define CCxxx0_FSCAL0 0x26 // Frequency synthesizer calibration
100 #define CCxxx0_RCCTRL1 0x27 // RC oscillator configuration
101 #define CCxxx0_RCCTRL0 0x28 // RC oscillator configuration
102 #define CCxxx0_FSTEST 0x29 // Frequency synthesizer calibration control
103 #define CCxxx0_PTEST 0x2A // Production test
104 #define CCxxx0_AGCTEST 0x2B // AGC test
105 #define CCxxx0_TEST2 0x2C // Various test settings
106 #define CCxxx0_TEST1 0x2D // Various test settings
107 #define CCxxx0_TEST0 0x2E // Various test settings
108
109 // Strobe commands
110 #define CCxxx0_SRES 0x30 // Reset chip.
111 #define CCxxx0_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL
-=1).
112 // If in RX/TX: Go to a wait state where only the synthesizer is
113 // running (for quick RX / TX turnaround).
114 #define CCxxx0_SXOFF 0x32 // Turn off crystal oscillator.
115 #define CCxxx0_SCAL 0x33 // Calibrate frequency synthesizer and turn it off
116 // (enables quick start).
C51 COMPILER V8.05a WIRELESS_CC1100RX 11/07/2007 15:16:42 PAGE 3
117 #define CCxxx0_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and
118 // MCSM0.FS_AUTOCAL=1.
119 #define CCxxx0_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if
120 // MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled:
121 // Only go to TX if channel is clear.
122 #define CCxxx0_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit
123 // Wake-On-Radio mode if applicable.
124 #define CCxxx0_SAFC 0x37 // Perform AFC adjustment of the frequency synthesizer
125 #define CCxxx0_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio)
126 #define CCxxx0_SPWD 0x39 // Enter power down mode when CSn goes high.
127 #define CCxxx0_SFRX 0x3A // Flush the RX FIFO buffer.
128 #define CCxxx0_SFTX 0x3B // Flush the TX FIFO buffer.
129 #define CCxxx0_SWORRST 0x3C // Reset real time clock.
130 #define CCxxx0_SNOP 0x3D // No operation. May be used to pad strobe commands to two
131 // bytes for simpler software.
132
133 #define CCxxx0_PARTNUM 0x30
134 #define CCxxx0_VERSION 0x31
135 #define CCxxx0_FREQEST 0x32
136 #define CCxxx0_LQI 0x33
137 #define CCxxx0_RSSI 0x34
138 #define CCxxx0_MARCSTATE 0x35
139 #define CCxxx0_WORTIME1 0x36
140 #define CCxxx0_WORTIME0 0x37
141 #define CCxxx0_PKTSTATUS 0x38
142 #define CCxxx0_VCO_VC_DAC 0x39
143 #define CCxxx0_TXBYTES 0x3A
144 #define CCxxx0_RXBYTES 0x3B
145
146 #define CCxxx0_PATABLE 0x3E
147 #define CCxxx0_TXFIFO 0x3F
148 #define CCxxx0_RXFIFO 0x3F
149
150
151
152 //-----------------------------------------------------------------------------
153 // 16-bit SFR Definitions for 'F33x
154 //-----------------------------------------------------------------------------
155
156 sfr16 DP = 0x82; // data pointer
157 sfr16 TMR3RL = 0x92; // Timer3 reload value
158 sfr16 TMR3 = 0x94; // Timer3 counter
159 sfr16 IDA0 = 0x96; // IDAC0 data
160 sfr16 ADC0 = 0xbd; // ADC0 data
161 sfr16 ADC0GT = 0xc3; // ADC0 Greater-Than
162 sfr16 ADC0LT = 0xc5; // ADC0 Less-Than
163 sfr16 TMR2RL = 0xca; // Timer2 reload value
164 sfr16 TMR2 = 0xcc; // Timer2 counter
165 sfr16 PCA0CP1 = 0xe9; // PCA0 Module 1 Capture/Compare
166 sfr16 PCA0CP2 = 0xeb; // PCA0 Module 2 Capture/Compare
167 sfr16 PCA0 = 0xf9; // PCA0 counter
168 sfr16 PCA0CP0 = 0xfb; // PCA0 Module 0 Capture/Compare
169
170
171
172 //-----------------------------------------------------------------------------
173 // Function PROTOTYPES
174
175 //-----------------------------------------------------------------------------
176 void SYSCLK_Init (void); // initialize system clock to 24.5 MHz
177 void PORT_Init (void); // initialize crossbar
178 void Timer1_Init(void); // interrupts enabled
C51 COMPILER V8.05a WIRELESS_CC1100RX 11/07/2007 15:16:42 PAGE 4
179 void Timer3_Init(unsigned int); // sets DAC output rate
180 void IDAC0_Init(void); // enables IDAC output on P0.1
181 void SPI_Init(void); // enable 3-wire Slave SPI for RF trans.
182 // DATA interface
183 void Variables_Init(void); // set global variables to reset values
184
185 void Timer3_ISR (void); // updates the DAC
186 void TIMER1_ISR(void);
187 // FIFO Routines
188 unsigned char ReceiveFIFO_Pull(); // pulls RXed compressed sample
189 unsigned short DACTXFIFO_Pull(); // pulls decompressed sample
190 void ReceiveFIFO_Push(unsigned char); // pushes RXed compressed sample
191 void DACTXFIFO_Push(unsigned short); // pushes decompressed sample
192 void CLEAR_FIFOS(void); // resets all FIFOs to default values
193
194 // DPCM Compression Algorithms
195 void DPCM_Decompress(void); // Compresses an ADC sample
196
197
198 //the mcu communicte with cc1100 by spi
199 //
200 void CCxxx0_Init(void);
201
202
203
204
205 unsigned char halSpiReadStatus(unsigned char addr);
206
207 void halSpiStrobe(unsigned char strobe);
208 void SPI_WAIT(void);
209 void POWER_UP_RESET_CCxxx0(void);
210 void halWait(int timeout);
211
212 void WaitMS(unsigned int);
213
214 void FIFO_ManagementRoutine(void); // encapsulates all foreground function
215 // calls concerning buffers, and
216 // all checks and tests on buffer
217 // sizes
218 void createDataPacket(unsigned char Counter_Pocket);
219
220 unsigned char halSpiReadReg(unsigned char addr);
221 void halSpiWriteReg(unsigned char addr, unsigned char value);
222 void halSpiReadBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count);
223 void halSpiWriteBurstReg(unsigned char addr, unsigned char *buffer,unsigned char count);
224 unsigned char ReceivePocket_Wait(void);
225 unsigned char halRfReceivePacket(unsigned char *RxTxBuffer, unsigned char *length);
226
227 //-----------------------------------------------------------------------------
228 // User-Defined Types
229 //-----------------------------------------------------------------------------
230
231
232 typedef union USHORT { // access a short variable as two
233 unsigned short S; // 8-bit integer values
234 unsigned char C[2];
235 } USHORT;
236
237 enum Logic{ FALSE, TRUE};
238
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