📄 wireless_cc1100rx.c.bak
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// Crystal accuracy = 40 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 541.666667 kHz
// Phase = 0
// Datarate = 249.938965 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 914.999969 MHz
// Channel spacing = 199.951172 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (2) Enable infinite length packets.
// Packetlength = 255
// Preamble count = (2) 4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (11) Serial Clock
unsigned char code RegValue[] = {
0x0A, // FSCTRL1 Frequency synthesizer control.
0x00, // FSCTRL0 Frequency synthesizer control.
0x23, // FREQ2 Frequency control word, high byte.
0x31, // FREQ1 Frequency control word, middle byte.
0x3B, // FREQ0 Frequency control word, low byte.
0x5D, // MDMCFG4 Modem configuration. 2D
0x3B, // MDMCFG3 Modem configuration.
0x73, // MDMCFG2 Modem configuration.
0x22, // MDMCFG1 Modem configuration.
0xF8, // MDMCFG0 Modem configuration.
0x00, // CHANNR Channel number.
0x00, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0xB6, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end RX configuration.
0x18, // MCSM0 Main Radio Control State Machine configuration. 18
0x1D, // FOCCFG Frequency Offset Compensation Configuration.
0x1C, // BSCFG Bit synchronization Configuration.
0xC7, // AGCCTRL2 AGC control.
0x00, // AGCCTRL1 AGC control.
0xB2, // AGCCTRL0 AGC control.
0xEA, // FSCAL3 Frequency synthesizer calibration.
0x2A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x1F, // FSCAL0 Frequency synthesizer calibration.
0x59, // FSTEST Frequency synthesizer calibration.
0x88, // TEST2 Various test settings.
0x31, // TEST1 Various test settings.
0x09, // TEST0 Various test settings.
0x06, // IOCFG2 GDO2 output pin configuration.
0x0B, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.
0x04, // PKTCTRL1 Packet automation control.
0x06, // PKTCTRL0 Packet automation control.
0x00, // ADDR Device address.
0xFF // PKTLEN Packet length.
};
// 1/2 Period Sine Wave Table
static char code Audio_SineTable[16] = {
0x00,0x18,0x30,0x47,0x5a,0x6a,0x76,0x7d,
0x7f,0x7d,0x76,0x6a,0x5a,0x47,0x30,0x18
};
// the mapping from DPCM quantization values to dpcm codes (array index)
short code Q_VALUES[16] = {0,
-high_high,
-high_mid,
-high_low,
-middle,
-low_high,
-low_mid,
-low_low,
0,
low_low,
low_mid,
low_high,
middle,
high_low,
high_mid,
high_high};
// CC1100 Interface Bits
sbit SCLK = P0^4; //SPI interface
sbit SO_data = P0^5;
sbit SI_data = P0^6;
sbit CSn = P0^7; //SPI interface
sbit GDO0 = P1^0;
sbit LEVEL1 = P1^2;
sbit LEVEL2 = P1^7;
sbit LEVEL3 = P1^6;
sbit LEVEL4 = P1^5;
// RX/TX State Machine variables, flags
void CLEAR_FIFOS(void); // resets all FIFOs to default values
bit RXTX_ResetVariables; // indicates to RF state machines that
// variables should be re-initialized
unsigned char RXTX_MasterSelect; // determines whether RF state machine
// behaves as slave or master across
// the RF link
bit RXTX_RunInitSlave; // signals RF state machine to run
// as slave
//int DAC_Error; // used to measure how far buffers are
// from defined ideal value
//int ADC_Error; // used to measure how far buffers are
// from defined ideal value
Audio_States Audio_LocalState; // shows whether audio signal is
Audio_States Audio_RemoteState; // "quiet" or "loud"
bit RXTX_Indicator; // shows whether RF state machine is in
// transmit or receive mode
bit OutputByteReady; // toggles to indicate whether both
// nibbles of OutputByte inside
// DPCM_Compress contain valid compressed
// data
// TransmitFIFO Variables
unsigned char TransmitFIFO_COUNT;
bit TransmitFIFO_EMPTY;
bit TransmitFIFO_OF;
bit TransmitFIFO_UF;
bit TransmitFIFO_FULL;
bit CC1020_StartUpCall;
unsigned char idata TransmitFIFO_FIRST;
unsigned char idata TransmitFIFO_LAST;
unsigned char xdata TransmitFIFO_FIFO[TransmitFIFO_FIFOSIZE];
// ReceiveFIFO Variables
unsigned char ReceiveFIFO_COUNT;
bit ReceiveFIFO_EMPTY;
bit ReceiveFIFO_OF;
bit ReceiveFIFO_UF;
bit ReceiveFIFO_FULL;
unsigned char idata ReceiveFIFO_FIRST;
unsigned char idata ReceiveFIFO_LAST;
unsigned char xdata ReceiveFIFO_FIFO[ReceiveFIFO_FIFOSIZE];
// ADCRXFIFO Variables
unsigned char ADCRXFIFO_COUNT;
bit ADCRXFIFO_EMPTY;
bit ADCRXFIFO_OF;
bit ADCRXFIFO_UF;
bit ADCRXFIFO_FULL;
unsigned char idata ADCRXFIFO_FIRST;
unsigned char idata ADCRXFIFO_LAST;
int xdata ADCRXFIFO_FIFO[ADCRXFIFO_FIFOSIZE];
// DACTXFIFO Variables
unsigned char DACTXFIFO_COUNT;
bit DACTXFIFO_EMPTY;
bit DACTXFIFO_OF;
bit DACTXFIFO_UF;
bit DACTXFIFO_FULL;
bit DACTXFIFO_DECOMPRESS_HALT;
unsigned char idata DACTXFIFO_FIRST;
unsigned char idata DACTXFIFO_LAST;
unsigned int xdata DACTXFIFO_FIFO[DACTXFIFO_FIFOSIZE];
unsigned char xdata RxTxBuffer[65];
//unsigned char xdata txBuffer[65];
//
bit txInProgress; // Set right before a STX strobe is transmitted. Cleared when
// radio enters IDLE mode (pktTxHandler())
//int txStartupTimeout; // Variable to keep track of bytes left in the txBuffer
bit rxTimeoutActive; // Set in the pktStartRx function if timeout != 0. Cleard in
// pktRxHandler() when pktData.rxTimeout reaches 0.
bit rxTimeoutReached; // Set when the Rx timeout is reached and RX mode is terminated.
//unsigned char txBytesLeft; // Variable holding information on number og bytes left in txBuffer
//int rxBytesLeft; // Variable to keep track of how many bytes are left to be received
bit pktTransmitted; // Flag set when there are no bytes left in the txBuffer
bit pktReceiving; // Flag set when a packet is received
bit pktReceive_Success;
bit lengthByteRead; //
//unsigned char pktFailure_Counter;
bit Search_Linker;
unsigned char length;
unsigned char code paTable[] = {0xc0};
//unsigned char Status;
short Receive_Pockets;
short Send_Pockets;
short Send_Pockets_bytes;
unsigned char Master_TH1_New;
unsigned char Master_TL1_New;
unsigned char Master_TH1_Old;
unsigned char Master_TL1_Old;
unsigned char Slave_TH1_New;
unsigned char Slave_TL1_New;
unsigned char Slave_TH1_Old;
unsigned char Slave_TL1_Old;
int Counter_ADC;
int Compress_Bytes;
short ReciveCompress_Bytes;
short Counters_DAC;
short Decompress_Bytes;
short DAC_Send;
short Counter_Lost;
unsigned char HopFre_Sequency_Nub;
unsigned char xdata hopTable[30];
unsigned char xdata activeTable[30];
unsigned char syncTable[4]= {16,48,80,112};
void Fre_Register_Setting(unsigned char Channel_Num);
unsigned char isSyncCh(unsigned char ch);
unsigned char isActiveCh(unsigned char ch);
unsigned char isHopCh(unsigned char ch);
void generateNewHopSeq (int seed);
//-----------------------------------------------------------------------------
// MAIN Routine
//-----------------------------------------------------------------------------
void main (void) {
unsigned char Counter;
Receive_Pockets = 0;
Send_Pockets = 0;
Send_Pockets_bytes = 0;
ReciveCompress_Bytes = 0;
Counters_DAC = 0;
DAC_Send = 0;
Decompress_Bytes = 0;
Counter_ADC =0;
Compress_Bytes = 0;
HopFre_Sequency_Nub = 0;
// unsigned char Register_Value;
PCA0MD &= ~0x40; // disable watchdog timer
PORT_Init(); // initialize and enable the Crossbar
SYSCLK_Init(); // initialize oscillator
SPI_Init(); // init
Timer1_Init();
Timer2_Init(SYSCLK/SAMPLE_RATE); // initialize timer to overflow
// at SAMPLE_RATE
halWait(80); // there are 80uS space between time2 and time3
Timer3_Init(SYSCLK/DAC_UPDATERATE); // initialize timer 3 to overflow at
// DACUPDATERATE
IDAC0_Init(); // enable DAC outputs at P0.1
Variables_Init();
WaitMS(500);
POWER_UP_RESET_CCxxx0();
CCxxx0_Init(); // initalize the RF transceiver
halSpiWriteBurstReg(CCxxx0_PATABLE, paTable, sizeof(paTable));
WaitMS(200);
RXTX_MasterSelect=RXTX_Searching;
generateNewHopSeq (34568);
EA = 1; // enables all interrupts
RXTX_RunInitSlave = TRUE;
HopFre_Sequency_Nub = 0;
Fre_Register_Setting(hopTable[HopFre_Sequency_Nub]);
halSpiStrobe(CCxxx0_SFRX);
//////////////////////////////////////////////////////////////////////////
Fre_Register_Setting(0);
halSpiStrobe(CCxxx0_SRX);
WaitMS(500);
length=65;
/////////////////////////////////////////////////////////////////////////////////
while (1)
{
if(ReceivePocket_Wait())
{
TH1 = 0xF9;
TL1 = 0x33;
if (halRfReceivePacket(RxTxBuffer, &length) )
{
for(Counter=4;Counter<62;Counter++) //4----=59
{ReceiveFIFO_Push(RxTxBuffer[Counter]);
ReciveCompress_Bytes ++;}
}
}
} // end while(1)
} // end void main()
//-----------------------------------------------------------------------------
// Initialization Functions
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
// SYSCLK_Init
//-----------------------------------------------------------------------------
//
// This routine initializes the system clock to use the internal 24.5MHz
// oscillator as its clock source. Also enables missing clock detector
// reset and enables the VDD monitor as a reset source.
//
void SYSCLK_Init (void)
{
unsigned char i;
unsigned char OSCstate;
P0&=0xF3;
OSCICN |= 0x03; // set clock to 24MHz
for(i=0;i<20;i++);
while(!(OSCXCN | 0x80));
OSCXCN = 0x67;
for(i=0;i<20;i++);//WaitMS(2);
do{
OSCstate = OSCXCN;
OSCstate &=0x80;
}while(OSCstate==80);
OSCICN |= 0x00; // set clock to 24.0 MHz
// CLKSEL = 0x01;
RSTSRC = 0x06; // enable missing clock detector
}
//-----------------------------------------------------------------------------
// PORT_Init
//-----------------------------------------------------------------------------
//
// P0.0 - VREF
// P0.1 - IDAC0 Output
// P0.2 - PSEL
// P0.3 - PCLK
// P0.4 -
// P0.5 -
// P0.6 - PDI
// P0.7 - PDO
// P1.0 - SCK (DCLK)
// P1.1 - MISO (DIO)
// P1.2 - MOSI (DIO)
// P1.3 - Audio Input
// P1.4 - Test Point
// P1.5 - LED1
// P1.6 - LED2
// P1.7 - Switch
void PORT_Init (void)
{
XBR0 |= 0x02;
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