usbohci.h

VxWorks源码

#define OHCI_RHS_CRWE		0x80000000  /* clear remote wakeup enable */
#define OHCI_RHS_CLR_RWE	0x80000000  /* write '1' to clear wakeup enable */


/* OHCI_RH_PORT_STATUS register(s) */

#define OHCI_RHPS_CCS		0x00000001  /* current connect status */
#define OHCI_RHPS_CLR_PE	0x00000001  /* write '1' to clear port enable */
#define OHCI_RHPS_PES		0x00000002  /* port enable status */
#define OHCI_RHPS_SET_PE	0x00000002  /* write '1' to set port enable */
#define OHCI_RHPS_PSS		0x00000004  /* port suspend status */
#define OHCI_RHPS_SET_PS	0x00000004  /* write '1' to set port suspend */
#define OHCI_RHPS_POCI		0x00000008  /* port over current indicator */
#define OHCI_RHPS_CLR_PS	0x00000008  /* write '1' to clear port suspend */
#define OHCI_RHPS_PRS		0x00000010  /* port reset status */
#define OHCI_RHPS_PPS		0x00000100  /* port power status */
#define OHCI_RHPS_SET_PWR	0x00000100  /* write '1' to set port power */
#define OHCI_RHPS_LSDA		0x00000200  /* low speed device attached */
#define OHCI_RHPS_CLR_PWR	0x00000200  /* write '1' to clear port power */
#define OHCI_RHPS_CSC		0x00010000  /* connect status change */
#define OHCI_RHPS_PESC		0x00020000  /* port enable status change */
#define OHCI_RHPS_PSSC		0x00040000  /* port suspend status change */
#define OHCI_RHPS_OCIC		0x00080000  /* port over current indicator chg */
#define OHCI_RHPS_PRSC		0x00100000  /* port reset status change */


/* OHCI_ED - OHCI Endpoint Descriptor
 *
 * NOTE: OHCI_ED must be aligned to a 16-byte boundary,
 */

#define OHCI_ED_ALIGNMENT	16	    /* alignment */

typedef struct ohci_ed
    {
    UINT32 control;		    /* control word */
    UINT32 tdTail;		    /* TD queue tail pointer */
    UINT32 tdHead;		    /* TD queue head pointer */
    UINT32 nextEd;		    /* next OHCI_ED */
    } OHCI_ED, *pOHCI_ED;   

#define OHCI_ED_LEN		16  /* expected size of OHCI_ED */
#define OHCI_ED_ACTLEN		sizeof (OHCI_ED)    /* actual */


/* OHCI_ED.control definitions */

#define OHCI_EDCTL_FA_MASK	0x0000007f  /* function address */
#define OHCI_EDCTL_FA_ROT	0

#define OHCI_EDCTL_EN_MASK	0x00000780  /* endpoint number */
#define OHCI_EDCTL_EN_ROT	7

#define OHCI_EDCTL_DIR_MASK	0x00001800  /* direction */
#define OHCI_EDCTL_DIR_TD	0x00000000  /* get direction from TD */
#define OHCI_EDCTL_DIR_OUT	0x00000800  /* OUT */
#define OHCI_EDCTL_DIR_IN	0x00001000  /* get direction from TD */

#define OHCI_EDCTL_SPD_MASK	0x00002000  /* speed */
#define OHCI_EDCTL_SPD_FULL	0x00000000  /* full speed (12mbit) device */
#define OHCI_EDCTL_SPD_LOW	0x00002000  /* low speed device */

#define OHCI_EDCTL_SKIP 	0x00004000  /* skip ED */

#define OHCI_EDCTL_FMT_MASK	0x00008000  /* TD format */
#define OHCI_EDCTL_FMT_GEN	0x00000000  /* general: ctl/bulk/int */
#define OHCI_EDCTL_FMT_ISO	0x00008000  /* isochronous TDs */

#define OHCI_EDCTL_MPS_MASK	0x07ff0000  /* maximum packet size */
#define OHCI_EDCTL_MPS_ROT	16

/* macros to format/retrieve control.FA (function address) field */

#define OHCI_EDCTL_FA(x)     (((x) & OHCI_EDCTL_FA_MASK) >> OHCI_EDCTL_FA_ROT)
#define OHCI_EDCTL_FA_FMT(x) (((x) << OHCI_EDCTL_FA_ROT) & OHCI_EDCTL_FA_MASK)

/* macros to format/retrieve control.EN (endpoint number) field */

#define OHCI_EDCTL_EN(x)     (((x) & OHCI_EDCTL_EN_MASK) >> OHCI_EDCTL_EN_ROT)
#define OHCI_EDCTL_EN_FMT(x) (((x) << OHCI_EDCTL_EN_ROT) & OHCI_EDCTL_EN_MASK)

/* macros to format/retrieve control.MPS (max packet size) field */

#define OHCI_EDCTL_MPS(x)     (((x) & OHCI_EDCTL_MPS_MASK) >> OHCI_EDCTL_MPS_ROT)
#define OHCI_EDCTL_MPS_FMT(x) (((x) << OHCI_EDCTL_MPS_ROT) & OHCI_EDCTL_MPS_MASK)


/* Memory pointer definitions.
 *
 * NOTE: Some/all of these definitions apply to the OHCI_ED.tdTail, tdHead, and 
 * nextEd fields.
 */

#define OHCI_PTR_MEM_MASK	0xfffffff0  /* mask for memory pointer */
#define OHCI_PTR_HALTED 	0x00000001  /* indicates TD queue is halted */
#define OHCI_PTR_TGL_CARRY	0x00000002  /* toggle carry */

#define OHCI_PAGE_SIZE		0x00001000  /* 4k pages */
#define OHCI_PAGE_MASK		0xfffff000  /* page # mask */

#define OHCI_ISO_OFFSET_MASK	0x00000fff  /* mask for 4k page */
#define OHCI_ISO_OFFSET_BP0	0x00000000  /* offset within BufferPage0 page */
#define OHCI_ISO_OFFSET_BE	0x00001000  /* offset within BufferEnd page */


/* OHCI_TD_GEN - OHCI Transfer Descriptor - General: Ctl/Bulk/Int 
 *
 * NOTE: Must be aligned to 16 byte boundary.
 */

#define OHCI_TD_GEN_ALIGNMENT	16	    /* alignment */

typedef struct ohci_td_gen
    {
    UINT32 control;		    /* control word */
    UINT32 cbp; 		    /* current buffer pointer */
    UINT32 nextTd;		    /* next TD */
    UINT32 be;			    /* buffer end */
    } OHCI_TD_GEN, *pOHCI_TD_GEN;

#define OHCI_TD_GEN_LEN 	    16	/* expected size of OHCI_TD_ISO */
#define OHCI_TD_GEN_ACTLEN	    sizeof (OHCI_TD_GEN)    /* actual */


/* OHCI_TD_GEN.control definitions */

#define OHCI_TGCTL_BFR_RND	0x00040000  /* buffer rounding */

#define OHCI_TGCTL_PID_MASK	0x00180000  /* direction/PID */
#define OHCI_TGCTL_PID_SETUP	0x00000000  /* SETUP */
#define OHCI_TGCTL_PID_OUT	0x00080000  /* OUT */
#define OHCI_TGCTL_PID_IN	0x00100000  /* IN */

#define OHCI_TGCTL_DI_MASK	0x00e00000  /* delay interrupt */
#define OHCI_TGCTL_DI_ROT	21
#define OHCI_TGCTL_DI_NONE	7

#define OHCI_TGCTL_TOGGLE_DATA0 0x00000000  /* indicates DATA0 */
#define OHCI_TGCTL_TOGGLE_DATA1 0x01000000  /* indicates DATA1 */
#define OHCI_TGCTL_TOGGLE_USEED 0x00000000  /* use toggle from ED */
#define OHCI_TGCTL_TOGGLE_USETD 0x02000000  /* use toggle from TD */

#define OHCI_TGCTL_ERRCNT_MASK	0x0c000000  /* error count */

#define OHCI_TGCTL_CC_MASK	0xf0000000  /* condition code */
#define OHCI_TGCTL_CC_ROT	28

/* macros to format/retrieve control.DI (delay interrupt) field */

#define OHCI_TGCTL_DI(x)     (((x) & OHCI_TGCTL_DI_MASK) >> OHCI_TGCTL_DI_ROT)
#define OHCI_TGCTL_DI_FMT(x) (((x) << OHCI_TGCTL_DI_ROT) & OHCI_TGCTL_DI_MASK)

/* macro to retrieve control.CC (completion code) field */

#define OHCI_TGCTL_CC(x)    (((x) & OHCI_TGCTL_CC_MASK) >> OHCI_TGCTL_CC_ROT)


/* OHCI_TD_ISO - OHCI Transfer Descriptor - Isochronous 
 *
 * NOTE: Must be aligned to 32 byte boundary.
 */

#define OHCI_TD_ISO_ALIGNMENT	32	    /* alignment */
#define OHCI_ISO_PSW_CNT	8	    /* count of pkt status words */

typedef struct ohci_td_iso
    {
    UINT32 control;		    /* control word */
    UINT32 bp0; 		    /* buffer page 0 */
    UINT32 nextTd;		    /* next TD */
    UINT32 be;			    /* buffer end */
    UINT16 psw [OHCI_ISO_PSW_CNT];  /* array of packet status words */
    } OHCI_TD_ISO, *pOHCI_TD_ISO;

#define OHCI_TD_ISO_LEN 	32  /* expected size of OHCI_TD_ISO */
#define OHCI_TD_ISO_ACTLEN	sizeof (OHCI_TD_ISO)	/* actual */


/* OHCI_TD_ISO.control definitions */

#define OHCI_TICTL_SF_MASK	0x0000ffff  /* starting frame */
#define OHCI_TICTL_SF_ROT	0

#define OHCI_TICTL_DI_MASK	0x00e00000  /* delay interrupt */
#define OHCI_TICTL_DI_ROT	21
#define OHCI_TICTL_DI_NONE	7

#define OHCI_TICTL_FC_MASK	0x07000000  /* frame count */
#define OHCI_TICTL_FC_ROT	24
#define OHCI_FC_SIZE_MASK	0x7	    /* mask for 3-bit count */

#define OHCI_TICTL_CC_MASK	0xf0000000  /* condition code */
#define OHCI_TICTL_CC_ROT	28

/* macros to format/retrieve control.SF (starting frame) field */

#define OHCI_TICTL_SF(x)     (((x) & OHCI_TICTL_SF_MASK) >> OHCI_TICTL_SF_ROT)
#define OHCI_TICTL_SF_FMT(x) (((x) << OHCI_TICTL_SF_ROT) & OHCI_TICTL_SF_MASK)

/* Macros to retrieve/format control.FC (frame count) field
 *
 * NOTE: OHCI frame count is one less than the real frame count. The macros 
 * compensate automatically.
 */

#define OHCI_TICTL_FC(x)     ((((x) & OHCI_TICTL_FC_MASK) >> OHCI_TICTL_FC_ROT) + 1)
#define OHCI_TICTL_FC_FMT(x) ((((x) - 1) & OHCI_FC_SIZE_MASK) << OHCI_TICTL_FC_ROT)

/* macro to retrieve control.CC (completion code) field */

#define OHCI_TICTL_CC(x)    (((x) & OHCI_TICTL_CC_MASK) >> OHCI_TICTL_CC_ROT)


/* OHCI_TD_ISO.psw definitions */

#define OHCI_TIPSW_SIZE_MASK	0x07ff	    /* size of packet */
#define OHCI_TIPSW_SIZE_ROT	0

#define OHCI_TIPSW_CC_MASK	0xf000	    /* completion code */
#define OHCI_TIPSW_CC_ROT	12

/* macro to retrieve psw.size field */

#define OHCI_TIPSW_SIZE(x)  (((x) & OHCI_TIPSW_SIZE_MASK) >> OHCI_TIPSW_SIZE_ROT)

/* macro to retrieve psw.CC (completion code) field */

#define OHCI_TIPSW_CC(x)     (((x) & OHCI_TIPSW_CC_MASK) >> OHCI_TIPSW_CC_ROT)
#define OHCI_TIPSW_CC_FMT(x) (((x) << OHCI_TIPSW_CC_ROT) & OHCI_TIPSW_CC_MASK)


/* OHCI_HCCA - Host Controller Communications Area
 *
 * NOTE: This structure must be aligned to a 256 byte boundary.
 */

#define OHCI_HCCA_ALIGNMENT	256	    /* HCCA alignment requirement */
#define OHCI_INT_ED_COUNT	32	    /* count of interrupt ED heads */
#define OHCI_HCCA_HC_RESERVED	120	    /* count of reserved bytes */
#define OHCI_HCCA_LEN		256	    /* expected size of structure */

typedef struct ohci_hcca
    {
    UINT32 intEdTable [OHCI_INT_ED_COUNT];  /* ptrs to interrupt EDs */
    UINT16 frameNo;			    /* frame no in low 16-bits */
    UINT16 pad1;			    /* set to 0 when updating frameNo */
    UINT32 doneHead;			    /* ptr to first completed TD */
    UINT8 hcReserved [OHCI_HCCA_HC_RESERVED]; /* reserved by HC */
    } OHCI_HCCA, *pOHCI_HCCA;

#define OHCI_HCCA_LEN		256	    /* expected size of structure */
#define OHCI_HCCA_ACTLEN	sizeof (OHCI_HCCA)  /* actual size */


/* If the low bit of the doneHead field is written as '1' by the HC, then
 * an additional interrupt condition is present and the host controller driver
 * should interrogate the HcInterruptStatus register to determine the cause.
 */

#define OHCI_DONE_HEAD_OTHER_INT    0x00000001


#ifdef	__cplusplus
}
#endif

#endif	/* __INCusbOhcih */


/* End of file. */