ppc403.h

VxWorks源码

#define _PPC403_DMACR2 0xd0	/* dma channel control register 2 (r/w) */
#define _PPC403_DMACR3 0xd8	/* dma channel control register 3 (r/w) */
#define _PPC403_DMACT0 0xc1	/* dma count register 0 (r/w) */
#define _PPC403_DMACT1 0xc9	/* dma count register 1 (r/w) */
#define _PPC403_DMACT2 0xd1	/* dma count register 2 (r/w) */
#define _PPC403_DMACT3 0xd9	/* dma count register 3 (r/w) */
#define _PPC403_DMADA0 0xc2	/* dma destination address register 0 (r/w) */
#define _PPC403_DMADA1 0xca	/* dma destination address register 1 (r/w) */
#define _PPC403_DMADA2 0xd2	/* dma destination address register 2 (r/w) */
#define _PPC403_DMADA3 0xda	/* dma destination address register 3 (r/w) */
#define _PPC403_DMASA0 0xc3	/* dma source address register 0 (r/w) */
#define _PPC403_DMASA1 0xcb	/* dma source address register 1 (r/w) */
#define _PPC403_DMASA2 0xd3	/* dma source address register 2 (r/w) */
#define _PPC403_DMASA3 0xdb	/* dma source address register 3 (r/w) */
#define _PPC403_DMASR  0xe0	/* dma status register (r/w) */

#define _PPC403_EXISR  0x40	/* external interrupt status register (r/w) */
#define _PPC403_EXIER  0x42	/* external interrupt enable register (r/w) */
#define _PPC403_IOCR   0xa0	/* input/output configuration register (r/w) */

/* time control register */

#define _PPC403_TCR_WPM_U	0xc000	/* watchdog period mask */
#define _PPC403_TCR_WRCM_U	0x3000	/* wotchdog reset control */
#define _PPC403_TCR_WIEM_U	0x0800	/* watchdog interrupt enable */
#define _PPC403_TCR_PIEM_U	0x0400	/* pit interupt enable */
#define _PPC403_TCR_FPM_U	0x0300	/* fit period */
#define _PPC403_TCR_FIEM_U	0x0080	/* fit interrupt enable */

/* timer control register */

#define _PPC403_TCR_WPM_U	0xc000	/* watchdog period */
#define _PPC403_TCR_WRCM_U	0x3000	/* watchdog reset control */
#define _PPC403_TCR_WIEM_U	0x0800	/* watchdog interrupt enable */
#define _PPC403_TCR_PIEM_U	0x0400	/* pit interrupt enable */
#define _PPC403_TCR_FP_U	0x0300	/* fit period */
#define _PPC403_TCR_FIE_U	0x0080	/* fit interrupt enable */
#define _PPC403_TCR_ARE_U	0x0040	/* fit auto-reload enable */

/* timer status register */

#define _PPC403_TSR_SNWM_U	0x8000	/* supress next watchdog */
#define _PPC403_TSR_WISM_U	0x4000	/* watchdog interrupt status */
#define _PPC403_TSR_WRSM_U	0x3000	/* watchdog reset status */
#define _PPC403_TSR_PISM_U	0x0800	/* pit interrupt status */
#define _PPC403_TSR_FISM_U	0x0400	/* fit interrupt status */


/* defintion of external interrupt status and enable registers' mask bits */
/* Interrupts are enabled by setting the corresponding bits in the EXIER  */
/* When interrupts occur, the corresponding bits in EXISR are set to one. */

#define _PPC403_EXI_CI	0x80000000	/* critical interrupt */
#define _PPC403_EXI_SRI	0x08000000	/* serial port receiver interrupt */
#define _PPC403_EXI_STI	0x04000000	/* serial port transmitter interrupt */
#define _PPC403_EXI_JRI	0x02000000	/* JTAG serial port receiver */
#define _PPC403_EXI_JTI	0x01000000	/* JTAG serial port receiver */
#define _PPC403_EXI_D0I	0x00800000	/* dma channel 0 */
#define _PPC403_EXI_D1I	0x00400000	/* dma channel 1 */
#define _PPC403_EXI_D2I	0x00200000	/* dma channel 2 */
#define _PPC403_EXI_D3I	0x00100000	/* dma channel 3 */
#define _PPC403_EXI_E0I	0x00000010	/* external interrupt0 */
#define _PPC403_EXI_E1I	0x00000008	/* external interrupt1 */
#define _PPC403_EXI_E2I	0x00000004	/* external interrupt2 */
#define _PPC403_EXI_E3I	0x00000002	/* external interrupt3 */
#define _PPC403_EXI_E4I	0x00000001	/* external interrupt4 */


#define	_PPC403_IOCR_E0TM	0x80000000  /* external intr 0 triggering */
					    /* 0 - level sensitive */
					    /* 1 - edge triggered */
#define	_PPC403_IOCR_E0LM	0x40000000  /* external inter 0 active level */
#define	_PPC403_IOCR_E1TM	0x20000000  /* external intr 1 triggering */
#define	_PPC403_IOCR_E1LM	0x10000000  /* external intr 1 active level */
#define	_PPC403_IOCR_E2TM	0x08000000  /* external intr 2 triggering */
#define	_PPC403_IOCR_E2LM	0x04000000  /* external intr 2 active level */
#define	_PPC403_IOCR_E3TM	0x02000000  /* external intr 3 triggering */
#define	_PPC403_IOCR_E3LM	0x01000000  /* external intr 3 active level */
#define	_PPC403_IOCR_E4TM	0x00800000  /* external intr 4 triggering */
#define	_PPC403_IOCR_E4LM	0x00400000  /* external intr 4 active level */
#define	_PPC403_IOCR_EDT	0x00080000  /* enable dram tri-state (GCX) */
#define	_PPC403_IOCR_SOR	0x00040000  /* enable sampling data (GCX) */
#define	_PPC403_IOCR_EDO	0x00008000  /* EDO dram enable (GCX) */
#define	_PPC403_IOCR_2XC	0x00004000  /* clock double core enable (GCX) */
#define	_PPC403_IOCR_ATC	0x00002000  /* adress tri-state control */
#define	_PPC403_IOCR_SPD	0x00001000  /* static power disable */
#define	_PPC403_IOCR_BEM	0x00000800  /* byte enable mode  SRAM accesses*/
#define	_PPC403_IOCR_PTD	0x00000400  /* device-paced mode disable SRAM */
#define	_PPC403_IOCR_ARE	0x00000080  /* asynchronous ready enable SRAM */

#define	_PPC403_IOCR_DRCM	0x00000020  /* DRAM read on CAS */
#define	_PPC403_IOCR_RDMM	0x00000018  /* real time debug mode */
					    /* b'00 - trace status output disabled */
					    /* b'01 - program and bus status */
					    /* b'10 - program status and trace output */
					    /* b'11 - reserved */
#define	_PPC403_IOCR_RDM(n)	((n)<<3)    /* real time debug mode */
#define	_PPC403_IOCR_TCSM	0x00000004  /* timer clock source */
					    /* 0 - SysClk pin */
					    /* 1 - TimerClk pin */
#define	_PPC403_IOCR_SCSM	0x00000002  /* serial port clock source */
					    /* 0 - SysClk pin */
					    /* 1 - SerClk pin */
#define	_PPC403_IOCR_SPCM	0x00000001  /* serial port configuration */
					    /* 0 - DSR/DTR */
					    /* 1 - CTS/RTS */
/* exception syndrome register mask bits: 
 * 0 - error not occured 1 - error occured */

#define _PPC403_ESR_IMCPM 0x80000000  /* instr machine check protection */
#define _PPC403_ESR_IMCNM 0x40000000  /* instr machine check non-configured */
#define _PPC403_ESR_IMCBM 0x20000000  /* instr machine check bus error */
#define _PPC403_ESR_IMCTM 0x10000000  /* instr machine check timeout */
#define _PPC403_ESR_PEIM  0x08000000  /* program exception - illegal */
#define _PPC403_ESR_PEPM  0x04000000  /* program exception - previledged */
#define _PPC403_ESR_PETM  0x02000000  /* program exception - trap */
#define _PPC403_ESR_DST   0x00800000  /* data storage exception - store fault */
#define _PPC403_ESR_DIZ   0x00400000  /* data/inst storage exception - zone f.*/

/* bus error syndrome register mask bits: 0 - no eroor  1 - error occured */

#define _PPC403_BESR_DSESM	0x80000000  /* data-side error status */
#define _PPC403_BESR_DMESM	0x40000000  /* dma error status */
#define _PPC403_BESR_RWSM	0x20000000  /* read/write status */
					    /* 0 - write error */
					    /* 1 - read error */
#define _PPC403_BESR_ETM	0x1c000000  /* error type */
					    /* 000 - protection violation */
					    /* 001 - parity error (GCX) */
					    /* 010 - access to non configured bank */
					    /* 100 - active level error on bus eroor input pin */
					    /* 110 - bus time-out */
					    /* 111 - reserved */
/* exception vector prefix register */

#define _PPC403_EVPR_EVPM	0xffff0000  /* exception vector prefix mask */

/* common bits for sram and dram configuration */

#define _PPC403_BR_BASM	   0xff000000	/* base address select mask*/
#define _PPC403_BR_BAS(n)  ((n)<<24)	/* base address select */
#define _PPC403_BR_BSM	   0x00e00000	/* bank size mask */
#define _PPC403_BR_BS_1MB  0x00000000	/* bank size : 000 - 1MB */
#define _PPC403_BR_BS_2MB  0x00200000	/* bank size : 001 - 2MB */
#define _PPC403_BR_BS_4MB  0x00400000	/* bank size : 010 - 4MB */
#define _PPC403_BR_BS_8MB  0x00600000	/* bank size : 011 - 8MB */
#define _PPC403_BR_BS_16MB 0x00800000	/* bank size : 100 - 16MB */
#define _PPC403_BR_BS_32MB 0x00a00000	/* bank size : 101 - 32MB */
#define _PPC403_BR_BS_64MB 0x00c00000	/* bank size : 110 - 64MB */
#define _PPC403_BR_BUM	   0x00180000	/* bank usage mask */
#define _PPC403_BR_BU_DIS  0x00000000	/* bank usage: 00 - disable */ 
#define _PPC403_BR_BU_RO   0x00080000	/* bank usage: 01 - read only */ 
#define _PPC403_BR_BU_WO   0x00100000	/* bank usage: 10 - write only */ 
#define _PPC403_BR_BU_RW   0x00180000	/* bank usage: 11 - read/write only */ 
#define _PPC403_BR_SLFM	   0x00040000	/* sram-dram sequential line fill */
#define _PPC403_BR_BWM	   0x00018000	/* bus width mask */
#define _PPC403_BR_BW_8	   0x00000000	/* bus width 00 - 8 bit  */
#define _PPC403_BR_BW_16   0x00008000	/* bus width 01 - 16 bit */
#define _PPC403_BR_BW_32   0x00010000	/* bus width 10 - 32 bit */
#define _PPC403_BR_BW_64   0x00018000	/* bus width 11 - 64 bit */
#define _PPC403_BR_SDM	   0x00000001	/* sram-dram selection 0-dram 1-sram */

/* sram configuration (br0 - br7) */

#define _PPC403_BRS_BMEM   0x00020000	/* burst mode enable - 0 disabled */
#define _PPC403_BRS_REM	   0x00004000	/* ready enable - 0 disabled */
#define _PPC403_BRS_TWM	   0x00003f00	/* transfer wiat-contains the number
					 * of wait states inserted by the 
					 * processor into all transactions */
#define _PPC403_BRS_TWT(n)  ((n)<<8)	/* transfer wait states - non-burst */
#define _PPC403_BRS_FWM     0x00003c00	/* first wait states mask */
#define _PPC403_BRS_FWT(n)  ((N)<<10)	/* first wait states - burst */
#define _PPC403_BRS_BWM     0x00000300	/* burst wait states mask */
#define _PPC403_BRS_BWT(n)  ((N)<<10)	/* burst wait states */
#define _PPC403_BRS_CSTM    0x00000080	/* chip select on timing
					 * 0 - valid when address is valid
					 * 1 - valid one SysClk cycle after
					 * address is valid */
#define _PPC403_BRS_OETM 0x00000040	/* output enable on timing
					 * 0 - valid when chip select is valid
					 * 1 - valid one SysClk cycle after
					 * chip select is valid */
#define _PPC403_BRS_WBNM 0x00000020	/* write byte enable on timing
					 * 0 - valid one chip select is valid
					 * 1 - on SysClk Cycle after */
#define _PPC403_BRS_WBFM 0x00000010	/* write byte enable off on timing
					 * 0 - inactive when chip select 
					 *     becomes inactive
					 * 1 - inactive one SysClk cycle 
					 *     before chip select becoms
					 *     inactive */
#define _PPC403_BRS_THM	0x0000000e	/* transfer hold mask */
#define _PPC403_BRS_TH(n)  ((n)<<1)	/* transfer hold */

/* dram configuration (br4 - br7) */

#define _PPC403_BRD_ERM	 0x00020000	/* Early Ras Mode */
#define _PPC403_BRD_IEM	 0x00004000	/* internal/external multiplex */
#define _PPC403_BRD_RCTM 0x00002000	/* RAS active to CAS active timing */
#define _PPC403_BRD_ARMM 0x00001000	/* alternate refresh mode 
					 * 0 - normal refresh
					 * 1 - immediate or self refresh */
#define _PPC403_BRD_PMM	 0x00000800	/* page mode 
					 * 0 - single accesses only
					 * 1 - burst access supported */
#define _PPC403_BRD_FACM 0x00000600	/* first access timing mask */
#define	_PPC403_BRD_FAC(n) ((n)<<9)	/* first access timing */
#define _PPC403_BRD_BACM 0x00000180	/* burst access timing mask */
#define _PPC403_BRD_BAC(n) ((n)<<7)	/* burst access timing */
#define _PPC403_BRD_PPCM 0x00000040	/* precharge cycles */
#define _PPC403_BRD_RARM 0x00000020	/* RAS active during refresh
					 * 0 - one and half sysclk cycle
					 * 1 - two and half */
#define _PPC403_BRD_RRM	0x0000001e	/* refresh interval mask */
#define _PPC403_BRD_RR(n)  ((n)<<1)	/* refresh interval */

/* bank register high configuration (brh0 - brh7) */


#define _PPC403_BRH_PCE	0x80000000	/* parity check enable */

/* dma channel control register */

#define _DMACR_CE	0x80000000	/* channel enable */
#define _DMACR_CIE	0x40000000	/* channel interrupt enable */
#define _DMACR_TD	0x20000000	/* transfer direction */
#define _DMACR_PL	0x10000000	/* peripheral location */
#define _DMACR_PW_MASK  0x0c000000	/* peripheral width */
#define _DMACR_PW_BYTE 	0x00000000	/* byte */
#define _DMACR_PW_SHORT 0x04000000	/* halfword */
#define _DMACR_PW_WORD 	0x08000000	/* word */
#define _DMACR_PW_RES 	0x0c000000	/* reserved */
#define _DMACR_DAI	0x02000000	/* destination address increment */
#define _DMACR_SAI	0x01000000	/* source address increment */
#define _DMACR_CP	0x00800000	/* channel priority */
#define _DMACR_TM_M	0x00600000	/* transfer mode mask */
#define _DMACR_TM_B	0x00000000	/* buffered dma */
#define _DMACR_TM_F	0x00200000	/* fly-by dma */
#define _DMACR_TM_S	0x00400000	/* software initiated mem-to-mem dma */
#define _DMACR_TM_H	0x00600000	/* hardware initiated mem-to-mem dma */
#define _DMACR_PSC_M	0x00180000	/* peripheral setup cycles mask */
#define _DMACR_PSC_0	0x00000000	/* no cycles */
#define _DMACR_PSC_1	0x00080000	/* one cycles */
#define _DMACR_PSC_2	0x00100000	/* two cycles */
#define _DMACR_PSC_3	0x00180000	/* three cycles */
#define _DMACR_PWC_MASK	0x0007e000 	/* peripheral wait cycles mask */
#define _DMACR_PHC_MASK 0x00001c00	/* peripheral hold cycles */
#define _DMACR_ETD	0x00000200	/* eoc/tc pin direction */
#define _DMACR_TCE	0x00000100	/* terminal count enable 
					 * 0 - end-of-transfer input
					 * 1 - terminal count output
					 */
#define _DMACR_CH	0x00000080	/* chaining enable */
#define _DMACR_BME	0x00000040	/* burst mode enable  */
#define _DMACR_ECE	0x00000020	/* EOT chain mode enable */
#define _DMACR_TCD	0x00000010	/* TC chain mode disable */
#define _DMACR_PCE	0x00000008	/* parity check enable */

/* dma status registers */

#define _DMASR_CS0_MASK	0x80000000	/* channel 0 terminal status */
#define _DMASR_CS1_MASK	0x40000000	/* channel 1 terminal status */
#define _DMASR_CS2_MASK	0x20000000	/* channel 2 terminal status */
#define _DMASR_CS3_MASK	0x10000000	/* channel 3 terminal status */

#define _DMASR_TS0_MASK	0x08000000	/* channel 0 end-of-transfer status */
#define _DMASR_TS1_MASK	0x04000000	/* channel 1 end-of-transfer status */
#define _DMASR_TS2_MASK	0x02000000	/* channel 2 end-of-transfer status */
#define _DMASR_TS3_MASK	0x01000000	/* channel 3 end-of-transfer status */

#define _DMASR_RI0_MASK	0x00800000	/* channel 0 error status */
#define _DMASR_RI1_MASK	0x00400000	/* channel 1 error status */
#define _DMASR_RI2_MASK	0x00200000	/* channel 2 error status */
#define _DMASR_RI3_MASK	0x00100000	/* channel 3 error status */

#define _DMASR_IR0_MASK	0x00040000	/* internal dma reguest 0 */
#define _DMASR_IR1_MASK	0x00020000	/* internal dma reguest 1 */
#define _DMASR_IR2_MASK	0x00010000	/* internal dma reguest 2 */
#define _DMASR_IR3_MASK	0x00008000	/* internal dma reguest 3 */

#define _DMASR_ER0_MASK	0x00004000	/* external dma reguest 0 */
#define _DMASR_ER1_MASK	0x00002000	/* external dma reguest 1 */
#define _DMASR_ER2_MASK	0x00001000	/* external dma reguest 2 */
#define _DMASR_ER3_MASK	0x00000800	/* external dma reguest 3 */

#define _DMASR_CB0_MASK	0x00000400	/* channel 0 busy */
#define _DMASR_CB1_MASK	0x00000200	/* channel 1 busy */
#define _DMASR_CB2_MASK	0x00000100	/* channel 2 busy */
#define _DMASR_CB3_MASK	0x00000080	/* channel 3 busy */

#define _DMASR_CT0_MASK	0x00080000	/* chained transfer on channel 0 */
#define _DMASR_CT1_MASK 0x00000040      /* chained transfer on channel 1 */
#define _DMASR_CT2_MASK 0x00000020      /* chained transfer on channel 1 */
#define _DMASR_CT3_MASK 0x00000010      /* chained transfer on channel 1 */

/* PVR definition */

#define _PVR_FAM_MSK	0xfff00000	/* processor family mask*/
#define _PVR_MEM_MSK	0x000f0000	/* processor family member mask */
#define _PVR_CCF_MSK	0x0000f000	/* Core Configuration mask */
#define _PVR_PCF_MSK	0x00000f00	/* Peripheral Configuration mask */
#define _PVR_MAJ_MSK	0x000000f0	/* Major Change Level mask */
#define _PVR_MIN_MSK	0x0000000f	/* Minor Change Level mask */

#define _PVR_CONF_403GA	    0x0000	/* processor conf. bits for 403GA */
#define _PVR_CONF_403GC	    0x0002	/* processor conf. bits for 403GC */
#define _PVR_CONF_403GCX    0x0014	/* processor conf. bits for 403GCX */

#ifdef __cplusplus
}
#endif

#endif /* __INCppc403h */