ppc403.h

VxWorks源码

/* ppc403.h - PowerPC 403 specific header */

/* Copyright 1984-2002 Wind River Systems, Inc. */
/*
modification history
--------------------
01p,06dec02,pch  Add MSR bit number definitions
01o,13jun02,jtp  identify class of MMU support (SPR #78396)
01n,22nov01,pch  Add _WRS_STRICT_ALIGNMENT for target/src/ostool/loadElfLib.c,
		 and _WRS_NO_TGT_SHELL_FP for target/src/ostool/shell*
01m,21oct98,elg  added hardware breakpoints for PPC403
01l,18mar97,tam  redefined INT_MASK to mask MSR[CE] (SPR 8192). 
01k,24feb97,tam  added definitions for the PPC403GC and PPC403GCX. 
01j,03oct96,tam  added more definitions for the bank registers. 
01i,20sep96,tam  added _PPC403_ICCR_DEFAULT_VAL and _PPC403_ICCR_DEFAULT_VAL. 
01h,18jun96,tam  added defines for the PowerPC 403 debug registers. 
		 removed TBL/TBU and PVR macros. 
01g,17jun96,tpr  added defines PowerPC 403 specific.
01f,09may96,tam  added missing definitions for dma chained count registers (1-3)
01e,07mar96,tam  fix DMASR macro values. (spr# 6018) - added PVR definition.
01d,08feb96,kkk  fix iocr macro values. (spr# 5416)
01c,17feb95,yao  added macros for dma register.
01b,17jan95,yao  added macros for external interrupt enable/status register.  
		 added definitions for debug control/ status registers.
01a,17mar94,yao  written.
*/

#ifndef __INCppc403h
#define __INCppc403h

#ifdef __cplusplus
extern "C" {
#endif

/* INT_MASK definition (mask EE & CE bits) : overwrite the one in asmPpc.h */

#undef	INT_MASK
#define INT_MASK(src, des)	rlwinm  des, src, 0, 17, 15; \
				rlwinm  des, des, 0, 15, 13

/* Tell the loader this processor can't handle any misalignment */
#define	_WRS_STRICT_ALIGNMENT	1

/* No floating point support in target shell */
#define	_WRS_NO_TGT_SHELL_FP	1

/* No MMU support in architecture library */
#undef _WRS_TLB_MISS_CLASS_SW

/* MSR definitions */

#undef 	_PPC_MSR_POW_U		/* power managemnet not supported */
#undef 	_PPC_MSR_ILE_U		/* little endian mode not supported */
#undef 	_PPC_MSR_SF_U		/* 64 bit mode not implemented */

#undef 	_PPC_MSR_BE		/* branch trace not supported */
#undef 	_PPC_MSR_FE1		/* floating point not supported */
#undef 	_PPC_MSR_FE0		/* floating point not supported */
#undef 	_PPC_MSR_IT		/* instruction address translation unsupported*/
#undef 	_PPC_MSR_DT		/* data address translation unsupported */
#undef 	_PPC_MSR_RI		/* recoverable interrupt unsupported */
#undef 	_PPC_MSR_LE		/* little endian mode unsupported */
#undef 	_PPC_MSR_SE		/* single step unsupported */
#undef 	_PPC_MSR_FP		/* floating point unsupported */

#define	_PPC_MSR_WE_U	0x0004	/* wait state enable */
#define _PPC_MSR_CE_U	0x0002	/* critical interrupt enable */
#define _PPC_MSR_DE	0x0200	/* debug exception enable */
#define _PPC_MSR_IR	0x0020	/* instruction relocate (403GC/GCX) */
#define _PPC_MSR_DR	0x0010	/* data relocate (403GC/GCX) */
#define _PPC_MSR_PE	0x0008	/* protection enable */
#define _PPC_MSR_PX	0x0004	/* protection exclusive mode */
#define _PPC_MSR_CE	0x00020000	/* critical interrupt enable mask */

/* MSR bit number definitions */

#define _PPC_MSR_BIT_IR  	26	/* MSR Inst Translation bit - IR */
#define _PPC_MSR_BIT_DR  	27	/* MSR Data Translation bit - DR */

/* Device Control Register PowerPC403 specific */

#undef  DEC		/* decrementer not supported */

#define	BEAR	0x090	/* bus error adress register read/clear */
#define	BESR	0x091	/* bus error syndrome register read/clear */
#define	BR0	0x080	/* bank register 0 */
#define	BR1	0x081	/* bank register 1 */
#define	BR2	0x082	/* bank register 2 */
#define	BR3	0x083	/* bank register 3 */
#define	BR4	0x084	/* bank register 4 */
#define	BR5	0x085	/* bank register 5 */
#define	BR6	0x086	/* bank register 6 */
#define	BR7	0x087	/* bank register 7 */
#define	BRH0	0x070	/* bank register 0 high */
#define	BRH1	0x071	/* bank register 1 high */
#define	BRH2	0x072	/* bank register 2 high */
#define	BRH3	0x073	/* bank register 3 high */
#define	BRH4	0x074	/* bank register 4 high */
#define	BRH5	0x075	/* bank register 5 high */
#define	BRH6	0x076	/* bank register 6 high */
#define	BRH7	0x077	/* bank register 7 high */
#define DMACC0  0xc4	/* dma chained count 0 r/w */
#define DMACC1 	0xcc	/* dma chained count 1 r/w */
#define DMACC2 	0xd4	/* dma chained count 2 r/w */
#define DMACC3 	0xdc	/* dma chained count 3 r/w */
#define DMACR0 	0xc0	/* dma channel control register 0 r/w */
#define DMACR1 	0xc8	/* dma channel control register 1 r/w */
#define DMACR2 	0xd0	/* dma channel control register 2 r/w */
#define DMACR3	0xd8	/* dma channel control register 3 r/w */
#define DMACT0 	0xc1	/* dma count register 0 r/w */
#define DMACT1 	0xc9	/* dma count register 1 r/w */
#define DMACT2 	0xd1	/* dma count register 2 r/w */
#define DMACT3 	0xd9	/* dma count register 3 r/w */
#define DMADA0 	0xc2	/* dma destination address register 0 r/w */
#define DMADA1 	0xca	/* dma destination address register 1 r/w */
#define DMADA2 	0xd2	/* dma destination address register 2 r/w */
#define DMADA3 	0xda	/* dma destination address register 3 r/w */
#define DMASA0 	0xc3	/* dma source address register 0 r/w */
#define DMASA1 	0xcb	/* dma source address register 1 r/w */
#define DMASA2 	0xd3	/* dma source address register 2 r/w */
#define DMASA3 	0xdb	/* dma source address register 3 r/w */
#define DMASR  	0xe0	/* dma status register r/w */
#define	EXIER	0x42	/* external interrupt enable register r/w */
#define	EXISR	0x40	/* external interrupt status register r/c */
#define	IOCR	0x0a0	/* input/output configuration register r/w */

/* Special Purpose Register PowerPC403 specific */

#define CDBCR	0x3d7	/* cache debug control register r/w */
#define DAC1	0x3f6	/* data adress compare register 1 r/w */
#define DAC2	0x3f7	/* data adress compare register 2 r/w */
#define	DBSR	0x3f0	/* debug status register read/clear */
#define	DBCR	0x3f2	/* debug control register read/write */
#define	DCCR	0x3fa	/* data cache control register r/w */
#define DCWR    0x3ba	/* data cache write-thru register (PPC403GC) r/w */
#define	DEAR	0x3d5	/* data exception address registers r */
#define	ESR	0x3d4	/* exception syndrom register r/w */
#define	EVPR	0x3d6	/* exception prefix register r/w */
#define IAC1	0x3f4	/* instruction adress compare register 1 r/w */
#define IAC2	0x3f5	/* instruction adress compare register 2 r/w */
#define	ICCR	0x3fb	/* instruction cache cacheability register r/w */
#define	ICDBDR	0x3d3	/* instruction cache debug data register r */
#define	PBL1	0x3fc	/* protection bound lower 1 r/w */
#define	PBL2	0x3fe	/* protection bound lower 2 r/w */
#define	PBU1	0x3fd	/* protection bound upper 1 r/w */
#define	PBU2	0x3ff	/* protection bound upper 2 r/w */
#define	PID	0x3b1	/* process id (403GC/GCX) r */
#define	PIT	0x3db	/* programmable interval timer r/w */
#define SGR    	0x3b9	/* storage guarded register (PPC403GC) r/w */
#define	SRR2	0x3de	/* save/restore register 2 r/w */
#define	SRR3	0x3df	/* save/restore register 3 r/w */
#define	TBLO	0x3dd	/* time base low r/w */
#define	TBHI	0x3dc	/* time base high r/w */
#define	TCR	0x3da	/* timer control register r/w */
#define	TSR	0x3d8	/* timer status register read/clear */
#define	TSRS	0x3d9	/* timer status register set (set only) */
#define	ZPR	0x3b0	/* zone protection register (PPC403GC/GCX) r/w */

#define mtdcr(dcrn, rs) .long   (0x7c0001c3 | (rs << 21) | (dcrf << 11))

#define MTDCR		0x7c0001c3
#define MFDCR		0x7c000143
#define _EXISR_OP	0x00001000
#define _EXIER_OP	0x00021000
#define MFEXISR_P0	.long   0x7c601286
#define MTEXISR_P0	.long   0x7c601386
#define MFEXISR_P1	.long   0x7c801286
#define MTEXISR_P1	.long   0x7c801386
#define MTEXIER_P0	.long   0x7c621386
#define MFEXIER_P0	.long   0x7c621286
#define MTEXIER_P1	.long   0x7c811386
#define MTEXIER_P2	.long   0x7ca11386
#define MFEXIER_P1	.long   0x7c811286

#define MTBESR_P0	.long   0x7c712386
#define RFCI		.long   0x4c000066

/* defines for cache support */

#undef	_CACHE_ALIGN_SIZE
#define	_CACHE_ALIGN_SIZE	16	/* cache line size */

#define _ICACHE_LINE_NUM	64	/* 64 cache lines per set */
#define _DCACHE_LINE_NUM	32	/* 32 cache lines per set */

#define	_PPC403_ICCR_DEFAULT_VAL	0x80000001 /* def. inst. cachability */
#define	_PPC403_DCCR_DEFAULT_VAL	0x80000001 /* def. data cachability */

#define	CACHE_SAFE_ADRS(x)	((int) (x) | 0x80000000)
#define	CACHE_ORIG_ADRS(x)	((int) (x) & 0x7fffffff)

#define _PPC_CACHE_UNIFIED	FALSE	/* XXX */

/* 403ga specific special purpouse registers */

#define	_PPC403_DBSR	0x3f0	/* debug status register read/clear */
#define _PPC403_DCCR	0x3fa	/* data cache control register r/w */
#define _PPC403_DEAR	0x3d5	/*  data exception address registers r */
#define _PPC403_ESR	0x3d4	/* exception syndrom register r/w */
#define _PPC403_EVPR	0x3d6	/* exception prefix register r/w */
#define _PPC403_ICCR	0x3fb	/* instruction cache control register r/w */
#define _PPC403_PBL1	0x3fc	/* protection bound lower 1 r/w */
#define _PPC403_PBL2	0x3fe	/* protection bound lower 2 r/w */
#define _PPC403_PBU1	0x3fd	/* protection bound upper 1 r/w */
#define _PPC403_PBU2	0x3ff	/* protection bound upper 2 r/w */
#define _PPC403_PIT	0x3db	/* programmable interval timer r/w */
#define _PPC403_SRR2	0x3de	/* save/restore register 2 r/w */
#define _PPC403_SRR3	0x3df	/* save/restore register 3 r/w */
#define _PPC403_SGR    	0x3b9	/* storage guarded register (PPC403GC) r/w */
#define _PPC403_DCWR    0x3ba   /* data cache write-thru (PPC403GC)r/w */

/* debug control register */

#define _DBCR_EDM_U	0x8000		/* external debug mode */
#define _DBCR_IDM_U	0x4000		/* internal debug mode */
#define _DBCR_IC_U	0x0800		/* instruction completion debug event */
#define _DBCR_BT_U	0x0400		/* branch taken */
#define _DBCR_EDE_U	0x0200		/* exception debug event */
#define _DBCR_TDE_U	0x0100		/* trap debug event */
#define _DBCR_FT_U	0x0004		/* freeze timers on debug */
#define _DBCR_IA1_U	0x0002		/* instruction address compare 1 */
#define _DBCR_IA2_U	0x0001		/* instruction address compare 2 */
#define _DBCR_EDM	0x80000000	/* external debug mode */
#define _DBCR_IDM	0x40000000	/* internal debug mode */
#define _DBCR_IC	0x08000000	/* instruction completion debug event */
#define _DBCR_BT	0x04000000	/* branch taken */
#define _DBCR_EDE	0x02000000	/* exception debug event */
#define _DBCR_TDE	0x01000000	/* trap debug event */
#define _DBCR_FT	0x00040000	/* freeze timers on debug */
#define _DBCR_IA1	0x00020000	/* instruction address compare 1 */
#define _DBCR_IA2	0x00010000	/* instruction address compare 2 */
#define _DBCR_D1R	0x00008000	/* data address compare read 1 */
#define _DBCR_D1W	0x00004000	/* data address compare write 1 */
#define _DBCR_D2R	0x00000800	/* data address compare read 2 */
#define _DBCR_D2W	0x00000400	/* data address compare write 2 */
#define _DBCR_JOI	0x00000002	/* jtag serial outbound */
#define _DBCR_JII	0x00000001	/* jtag serial inbound */

/* set access from type in DBCR */

#define _DBCR_D1A(x)	(((x) & 0x03) << 14)	/* for first breakpoint */
#define _DBCR_D2A(x)	(((x) & 0x03) << 10)	/* for second breakpoint */

/* set size from type in DBCR */

#define _DBCR_D1S(x)	(((x) & 0x0C) << 10)	/* for first breakpoint */
#define _DBCR_D2S(x)	(((x) & 0x0C) << 6)	/* for first breakpoint */

/* get access from DBCR */

#define _DBCR_D1_ACCESS(x)	(((x) >> 14) & 0x03)
#define _DBCR_D2_ACCESS(x)	(((x) >> 10) & 0x03)

/* get size from DBCR */

#define _DBCR_D1_SIZE(x)	(((x) >> 10) & 0x0C)
#define _DBCR_D2_SIZE(x)	(((x) >> 6) & 0x0C)

/* debug status register */

#define _DBSR_IC_U	0x8000		/* instruction completion */
#define _DBSR_BT_U	0x4000		/* branch taken */
#define _DBSR_EXC_U	0x2000		/* exception debug */
#define _DBSR_TIE_U	0x1000		/* trap instruction */
#define _DBSR_UDE_U	0x0800		/* unconditional debug */
#define _DBSR_IA1_U	0x0400		/* instruction address compare 1 */
#define _DBSR_IA2_U	0x0200		/* instruction address compare 2 */
#define _DBSR_DR1_U	0x0100		/* data address compare read 1 */
#define _DBSR_DW1_U	0x0080		/* data address compare write 1 */
#define _DBSR_DR2_U	0x0040		/* data address compare read 2 */
#define _DBSR_DW2_U	0x0020		/* data address compare write 2 */
#define _DBSR_IDE_U	0x0010		/* imprecise debug */
#define _DBSR_IC	0x80000000	/* instruction completion */
#define _DBSR_BT	0x40000000	/* branch taken */
#define _DBSR_EXC	0x20000000	/* exception debug */
#define _DBSR_TIE	0x10000000	/* trap instruction */
#define _DBSR_UDE	0x08000000	/* unconditional debug */
#define _DBSR_IA1	0x04000000	/* instruction address compare 1 */
#define _DBSR_IA2	0x02000000	/* instruction address compare 2 */
#define _DBSR_DR1	0x01000000	/* data address compare read 1 */
#define _DBSR_DW1	0x00800000	/* data address compare write 1 */
#define _DBSR_DR2	0x00400000	/* data address compare read 2 */
#define _DBSR_DW2	0x00200000	/* data address compare write 2 */
#define _DBSR_IDE	0x00100000	/* imprecise debug */
#define _DBSR_MRRM	0x00000300	/* Most recent reset mask */
#define _DBSR_MRR(n)	((n) << 8) 	/* Most recent reset */
#define _DBSR_JIF	0x00000004	/* jtag serial inbound buffer full */
#define _DBSR_JIO	0x00000002	/* jtag serial inbound buffer overrun */
#define _DBSR_JOE	0x00000001	/* jtag serial outbound buffer empty */

/* mask for hardware breakpoints */

#define _DBSR_HWBP_MSK	(_DBSR_IA1 | _DBSR_IA2 | \
                         _DBSR_DR1 | _DBSR_DW1 | \
			 _DBSR_DR2 | _DBSR_DW2)

/* device control registers */

#define _PPC403_BEAR	0x90	/* bus error address register (read only) */
#define _PPC403_BESR	0x91	/* bus error syndrom register (r/w) */
#define _PPC403_BR0	0x80	/* bank register 0 (r/w) */
#define _PPC403_BR1	0x81	/* bank register 1 (r/w) */
#define _PPC403_BR2	0x82	/* bank register 2 (r/w) */
#define _PPC403_BR3	0x83	/* bank register 3 (r/w) */
#define _PPC403_BR4	0x84	/* bank register 4 (r/w) */
#define _PPC403_BR5	0x85	/* bank register 5 (r/w) */
#define _PPC403_BR6	0x86	/* bank register 6 (r/w) */
#define _PPC403_BR7	0x87	/* bank register 7 (r/w) */

#define _PPC403_DMACC0 0xc4	/* dma chained count 0 (r/w) */
#define _PPC403_DMACC1 0xcc     /* dma chained count 1 (r/w) */
#define _PPC403_DMACC2 0xd4     /* dma chained count 2 (r/w) */
#define _PPC403_DMACC3 0xdc     /* dma chained count 3 (r/w) */
#define _PPC403_DMACR0 0xc0	/* dma channel control register 0 (r/w) */
#define _PPC403_DMACR1 0xc8	/* dma channel control register 1 (r/w) */