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/* * This code initialises the E300 processor core * (conforms to PowerPC 603e spec) * Note: expects original MSR contents to be in r5. */ .globl init_e300_coreinit_e300_core: /* time t 10 */ /* Initialize machine status; enable machine check interrupt */ /*-----------------------------------------------------------*/ li r3, MSR_KERNEL /* Set ME and RI flags */ rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */#ifdef DEBUG rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */#endif SYNC /* Some chip revs need this... */ mtmsr r3 SYNC mtspr SRR1, r3 /* Make SRR1 match MSR */ lis r3, CFG_IMMR@h#if defined(CONFIG_WATCHDOG) /* Initialise the Wathcdog values and reset it (if req) */ /*------------------------------------------------------*/ lis r4, CFG_WATCHDOG_VALUE ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) stw r4, SWCRR(r3) /* and reset it */ li r4, 0x556C sth r4, SWSRR@l(r3) li r4, 0xAA39 sth r4, SWSRR@l(r3)#else /* Disable Wathcdog */ /*-------------------*/ lwz r4, SWCRR(r3) /* Check to see if its enabled for disabling once disabled by SW you can't re-enable */ andi. r4, r4, 0x4 beq 1f xor r4, r4, r4 stw r4, SWCRR(r3)1:#endif /* CONFIG_WATCHDOG */ /* Initialize the Hardware Implementation-dependent Registers */ /* HID0 also contains cache control */ /*------------------------------------------------------*/ lis r3, CFG_HID0_INIT@h ori r3, r3, CFG_HID0_INIT@l SYNC mtspr HID0, r3 lis r3, CFG_HID0_FINAL@h ori r3, r3, CFG_HID0_FINAL@l SYNC mtspr HID0, r3 lis r3, CFG_HID2@h ori r3, r3, CFG_HID2@l SYNC mtspr HID2, r3 /* clear all BAT's */ /*----------------------------------*/ xor r0, r0, r0 mtspr DBAT0U, r0 mtspr DBAT0L, r0 mtspr DBAT1U, r0 mtspr DBAT1L, r0 mtspr DBAT2U, r0 mtspr DBAT2L, r0 mtspr DBAT3U, r0 mtspr DBAT3L, r0 mtspr IBAT0U, r0 mtspr IBAT0L, r0 mtspr IBAT1U, r0 mtspr IBAT1L, r0 mtspr IBAT2U, r0 mtspr IBAT2L, r0 mtspr IBAT3U, r0 mtspr IBAT3L, r0 SYNC /* invalidate all tlb's * * From the 603e User Manual: "The 603e provides the ability to * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) * instruction invalidates the TLB entry indexed by the EA, and * operates on both the instruction and data TLBs simultaneously * invalidating four TLB entries (both sets in each TLB). The * index corresponds to bits 15-19 of the EA. To invalidate all * entries within both TLBs, 32 tlbie instructions should be * issued, incrementing this field by one each time." * * "Note that the tlbia instruction is not implemented on the * 603e." * * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 * incrementing by 0x1000 each time. The code below is sort of * based on code in "flush_tlbs" from arch/ppc/kernel/head.S * */ li r3, 32 mtctr r3 li r3, 01: tlbie r3 addi r3, r3, 0x1000 bdnz 1b SYNC /* Done! */ /*------------------------------*/ blr .globl invalidate_batsinvalidate_bats: /* invalidate BATs */ mtspr IBAT0U, r0 mtspr IBAT1U, r0 mtspr IBAT2U, r0 mtspr IBAT3U, r0#if (CFG_HID2 & HID2_HBE) mtspr IBAT4U, r0 mtspr IBAT5U, r0 mtspr IBAT6U, r0 mtspr IBAT7U, r0#endif isync mtspr DBAT0U, r0 mtspr DBAT1U, r0 mtspr DBAT2U, r0 mtspr DBAT3U, r0#if (CFG_HID2 & HID2_HBE) mtspr DBAT4U, r0 mtspr DBAT5U, r0 mtspr DBAT6U, r0 mtspr DBAT7U, r0#endif isync sync blr /* setup_bats - set them up to some initial state */ .globl setup_batssetup_bats: addis r0, r0, 0x0000 /* IBAT 0 */ addis r4, r0, CFG_IBAT0L@h ori r4, r4, CFG_IBAT0L@l addis r3, r0, CFG_IBAT0U@h ori r3, r3, CFG_IBAT0U@l mtspr IBAT0L, r4 mtspr IBAT0U, r3 isync /* DBAT 0 */ addis r4, r0, CFG_DBAT0L@h ori r4, r4, CFG_DBAT0L@l addis r3, r0, CFG_DBAT0U@h ori r3, r3, CFG_DBAT0U@l mtspr DBAT0L, r4 mtspr DBAT0U, r3 isync /* IBAT 1 */ addis r4, r0, CFG_IBAT1L@h ori r4, r4, CFG_IBAT1L@l addis r3, r0, CFG_IBAT1U@h ori r3, r3, CFG_IBAT1U@l mtspr IBAT1L, r4 mtspr IBAT1U, r3 isync /* DBAT 1 */ addis r4, r0, CFG_DBAT1L@h ori r4, r4, CFG_DBAT1L@l addis r3, r0, CFG_DBAT1U@h ori r3, r3, CFG_DBAT1U@l mtspr DBAT1L, r4 mtspr DBAT1U, r3 isync /* IBAT 2 */ addis r4, r0, CFG_IBAT2L@h ori r4, r4, CFG_IBAT2L@l addis r3, r0, CFG_IBAT2U@h ori r3, r3, CFG_IBAT2U@l mtspr IBAT2L, r4 mtspr IBAT2U, r3 isync /* DBAT 2 */ addis r4, r0, CFG_DBAT2L@h ori r4, r4, CFG_DBAT2L@l addis r3, r0, CFG_DBAT2U@h ori r3, r3, CFG_DBAT2U@l mtspr DBAT2L, r4 mtspr DBAT2U, r3 isync /* IBAT 3 */ addis r4, r0, CFG_IBAT3L@h ori r4, r4, CFG_IBAT3L@l addis r3, r0, CFG_IBAT3U@h ori r3, r3, CFG_IBAT3U@l mtspr IBAT3L, r4 mtspr IBAT3U, r3 isync /* DBAT 3 */ addis r4, r0, CFG_DBAT3L@h ori r4, r4, CFG_DBAT3L@l addis r3, r0, CFG_DBAT3U@h ori r3, r3, CFG_DBAT3U@l mtspr DBAT3L, r4 mtspr DBAT3U, r3 isync#if (CFG_HID2 & HID2_HBE) /* IBAT 4 */ addis r4, r0, CFG_IBAT4L@h ori r4, r4, CFG_IBAT4L@l addis r3, r0, CFG_IBAT4U@h ori r3, r3, CFG_IBAT4U@l mtspr IBAT4L, r4 mtspr IBAT4U, r3 isync /* DBAT 4 */ addis r4, r0, CFG_DBAT4L@h ori r4, r4, CFG_DBAT4L@l addis r3, r0, CFG_DBAT4U@h ori r3, r3, CFG_DBAT4U@l mtspr DBAT4L, r4 mtspr DBAT4U, r3 isync /* IBAT 5 */ addis r4, r0, CFG_IBAT5L@h ori r4, r4, CFG_IBAT5L@l addis r3, r0, CFG_IBAT5U@h ori r3, r3, CFG_IBAT5U@l mtspr IBAT5L, r4 mtspr IBAT5U, r3 isync /* DBAT 5 */ addis r4, r0, CFG_DBAT5L@h ori r4, r4, CFG_DBAT5L@l addis r3, r0, CFG_DBAT5U@h ori r3, r3, CFG_DBAT5U@l mtspr DBAT5L, r4 mtspr DBAT5U, r3 isync /* IBAT 6 */ addis r4, r0, CFG_IBAT6L@h ori r4, r4, CFG_IBAT6L@l addis r3, r0, CFG_IBAT6U@h ori r3, r3, CFG_IBAT6U@l mtspr IBAT6L, r4 mtspr IBAT6U, r3 isync /* DBAT 6 */ addis r4, r0, CFG_DBAT6L@h ori r4, r4, CFG_DBAT6L@l addis r3, r0, CFG_DBAT6U@h ori r3, r3, CFG_DBAT6U@l mtspr DBAT6L, r4 mtspr DBAT6U, r3 isync /* IBAT 7 */ addis r4, r0, CFG_IBAT7L@h ori r4, r4, CFG_IBAT7L@l addis r3, r0, CFG_IBAT7U@h ori r3, r3, CFG_IBAT7U@l mtspr IBAT7L, r4 mtspr IBAT7U, r3 isync /* DBAT 7 */ addis r4, r0, CFG_DBAT7L@h ori r4, r4, CFG_DBAT7L@l addis r3, r0, CFG_DBAT7U@h ori r3, r3, CFG_DBAT7U@l mtspr DBAT7L, r4 mtspr DBAT7U, r3 isync#endif /* Invalidate TLBs. * -> for (val = 0; val < 0x20000; val+=0x1000) * -> tlbie(val); */ lis r3, 0 lis r5, 21: tlbie r3 addi r3, r3, 0x1000 cmp 0, 0, r3, r5 blt 1b blr .globl enable_addr_transenable_addr_trans: /* enable address translation */ mfmsr r5 ori r5, r5, (MSR_IR | MSR_DR) mtmsr r5 isync blr .globl disable_addr_transdisable_addr_trans: /* disable address translation */ mflr r4 mfmsr r3 andi. r0, r3, (MSR_IR | MSR_DR) beqlr andc r3, r3, r0 mtspr SRR0, r4 mtspr SRR1, r3 rfi/* Cache functions. * * Note: requires that all cache bits in * HID0 are in the low half word. */ .globl icache_enableicache_enable: mfspr r3, HID0 ori r3, r3, HID0_ICE lis r4, 0 ori r4, r4, HID0_ILOCK andc r3, r3, r4 ori r4, r3, HID0_ICFI isync mtspr HID0, r4 /* sets enable and invalidate, clears lock */ isync mtspr HID0, r3 /* clears invalidate */ blr .globl icache_disableicache_disable: mfspr r3, HID0 lis r4, 0 ori r4, r4, HID0_ICE|HID0_ILOCK andc r3, r3, r4 ori r4, r3, HID0_ICFI isync mtspr HID0, r4 /* sets invalidate, clears enable and lock*/ isync mtspr HID0, r3 /* clears invalidate */ blr .globl icache_statusicache_status: mfspr r3, HID0 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 blr .globl dcache_enabledcache_enable: mfspr r3, HID0 li r5, HID0_DCFI|HID0_DLOCK andc r3, r3, r5 mtspr HID0, r3 /* no invalidate, unlock */ ori r3, r3, HID0_DCE ori r5, r3, HID0_DCFI mtspr HID0, r5 /* enable + invalidate */ mtspr HID0, r3 /* enable */ sync blr .globl dcache_disabledcache_disable: mfspr r3, HID0 lis r4, 0 ori r4, r4, HID0_DCE|HID0_DLOCK andc r3, r3, r4 ori r4, r3, HID0_DCI sync mtspr HID0, r4 /* sets invalidate, clears enable and lock */ sync mtspr HID0, r3 /* clears invalidate */ blr .globl dcache_statusdcache_status: mfspr r3, HID0 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 blr .globl get_pvrget_pvr: mfspr r3, PVR blr/*------------------------------------------------------------------------------- *//* Function: ppcDcbf *//* Description: Data Cache block flush *//* Input: r3 = effective address *//* Output: none. *//*------------------------------------------------------------------------------- */ .globl ppcDcbfppcDcbf: dcbf r0,r3 blr/*------------------------------------------------------------------------------- *//* Function: ppcDcbi *//* Description: Data Cache block Invalidate */⌨️ 快捷键说明
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