immap_83xx.h

from [e-mail] 电路原理图和详细说明： amd.9966.org或者 arm.9966.org 都是原创,包括boot, loader,u-boot,linu

#define EATCR_ERRTYPR_PEA	0x60000000	/* parity error indication received on a read */
#define EATCR_ERRTYPR_PEW	0x70000000	/* parity error indication received on a write */
#define EATCR_BN_MASK		0x0f000000	/* beat number */
#define EATCR_BN_1st		0x00000000
#define EATCR_BN_2ed		0x01000000
#define EATCR_BN_3rd		0x02000000
#define EATCR_BN_4th		0x03000000
#define EATCR_BN_5th		0x0400000
#define EATCR_BN_6th		0x05000000
#define EATCR_BN_7th		0x06000000
#define EATCR_BN_8th		0x07000000
#define EATCR_BN_9th		0x08000000
#define EATCR_TS_MASK		0x00300000	/* transaction size */
#define EATCR_TS_4		0x00000000
#define EATCR_TS_1		0x00100000
#define EATCR_TS_2		0x00200000
#define EATCR_TS_3		0x00300000
#define EATCR_ES_MASK		0x000f0000	/* error source */
#define EATCR_ES_EM		0x00000000	/* external master */
#define EATCR_ES_DMA		0x00050000
#define EATCR_CMD_MASK		0x0000f000
#if defined (CONFIG_MPC8349)
#define EATCR_HBE_MASK		0x00000f00	/* PCI high byte enable */
#endif
#define EATCR_BE_MASK		0x000000f0	/* PCI byte enable */
#if defined (CONFIG_MPC8349)
#define EATCR_HPB		0x00000004	/* high parity bit */
#endif
#define EATCR_PB		0x00000002	/* parity bit */
#define EATCR_VI		0x00000001	/* error information valid */
	u32 eacr;
	u32 eeacr;
#if defined (CONFIG_MPC8349)
	u32 edlcr;
	u32 edhcr;
#elif defined (CONFIG_MPC8360)
	u32 edcr;		/* was edlcr */
	u8 res_edcr[0x4];
#endif
	u32 gcr;
	u32 ecr;
	u32 gsr;
	u8 res0[12];
	u32 pitar2;
	u8 res1[4];
	u32 pibar2;
	u32 piebar2;
	u32 piwar2;
	u8 res2[4];
	u32 pitar1;
	u8 res3[4];
	u32 pibar1;
	u32 piebar1;
	u32 piwar1;
	u8 res4[4];
	u32 pitar0;
	u8 res5[4];
	u32 pibar0;
	u8 res6[4];
	u32 piwar0;
	u8 res7[132];
#define PITAR_TA_MASK		0x000fffff
#define PIBAR_MASK		0xffffffff
#define PIEBAR_EBA_MASK		0x000fffff
#define PIWAR_EN		0x80000000
#define PIWAR_PF		0x20000000
#define PIWAR_RTT_MASK		0x000f0000
#define PIWAR_RTT_NO_SNOOP	0x00040000
#define PIWAR_RTT_SNOOP		0x00050000
#define PIWAR_WTT_MASK		0x0000f000
#define PIWAR_WTT_NO_SNOOP	0x00004000
#define PIWAR_WTT_SNOOP		0x00005000
#define PIWAR_IWS_MASK	0x0000003F
#define PIWAR_IWS_4K	0x0000000B
#define PIWAR_IWS_8K	0x0000000C
#define PIWAR_IWS_16K	0x0000000D
#define PIWAR_IWS_32K	0x0000000E
#define PIWAR_IWS_64K	0x0000000F
#define PIWAR_IWS_128K	0x00000010
#define PIWAR_IWS_256K	0x00000011
#define PIWAR_IWS_512K	0x00000012
#define PIWAR_IWS_1M	0x00000013
#define PIWAR_IWS_2M	0x00000014
#define PIWAR_IWS_4M	0x00000015
#define PIWAR_IWS_8M	0x00000016
#define PIWAR_IWS_16M	0x00000017
#define PIWAR_IWS_32M	0x00000018
#define PIWAR_IWS_64M	0x00000019
#define PIWAR_IWS_128M	0x0000001A
#define PIWAR_IWS_256M	0x0000001B
#define PIWAR_IWS_512M	0x0000001C
#define PIWAR_IWS_1G	0x0000001D
#define PIWAR_IWS_2G	0x0000001E
} pcictrl83xx_t;

#if defined (CONFIG_MPC8349)
/*
 * USB
 */
typedef struct usb83xx {
	u8 fixme[0x2000];
} usb83xx_t;

/*
 * TSEC
 */
typedef struct tsec83xx {
	u8 fixme[0x1000];
} tsec83xx_t;
#endif

/*
 * Security
 */
typedef struct security83xx {
	u8 fixme[0x10000];
} security83xx_t;

#if defined (CONFIG_MPC8360)
/*
 * iram
 */
typedef struct iram83xx {
	u32 iadd;		/* I-RAM address register */
	u32 idata;		/* I-RAM data register */
	u8 res0[0x78];
} iram83xx_t;

/*
 * Interrupt Controller
 */
typedef struct irq83xx {
	u32 cicr;		/* QE system interrupt configuration */
	u32 civec;		/* QE system interrupt vector register */
	u32 cripnr;		/* QE RISC interrupt pending register */
	u32 cipnr;		/*  QE system interrupt pending register */
	u32 cipxcc;		/* QE interrupt priority register */
	u32 cipycc;		/* QE interrupt priority register */
	u32 cipwcc;		/* QE interrupt priority register */
	u32 cipzcc;		/* QE interrupt priority register */
	u32 cimr;		/* QE system interrupt mask register */
	u32 crimr;		/* QE RISC interrupt mask register */
	u32 cicnr;		/* QE system interrupt control register */
	u8 res0[0x4];
	u32 ciprta;		/* QE system interrupt priority register for RISC tasks A */
	u32 ciprtb;		/* QE system interrupt priority register for RISC tasks B */
	u8 res1[0x4];
	u32 cricr;		/* QE system RISC interrupt control */
	u8 res2[0x20];
	u32 chivec;		/* QE high system interrupt vector */
	u8 res3[0x1C];
} irq83xx_t;

/*
 * Communications Processor
 */
typedef struct cp83xx {
	u32 cecr;		/* QE command register */
	u32 ceccr;		/* QE controller configuration register */
	u32 cecdr;		/* QE command data register */
	u8 res0[0xA];
	u16 ceter;		/* QE timer event register */
	u8 res1[0x2];
	u16 cetmr;		/* QE timers mask register */
	u32 cetscr;		/* QE time-stamp timer control register */
	u32 cetsr1;		/* QE time-stamp register 1 */
	u32 cetsr2;		/* QE time-stamp register 2 */
	u8 res2[0x8];
	u32 cevter;		/* QE virtual tasks event register */
	u32 cevtmr;		/* QE virtual tasks mask register */
	u16 cercr;		/* QE RAM control register */
	u8 res3[0x2];
	u8 res4[0x24];
	u16 ceexe1;		/* QE external request 1 event register */
	u8 res5[0x2];
	u16 ceexm1;		/* QE external request 1 mask register */
	u8 res6[0x2];
	u16 ceexe2;		/* QE external request 2 event register */
	u8 res7[0x2];
	u16 ceexm2;		/* QE external request 2 mask register */
	u8 res8[0x2];
	u16 ceexe3;		/* QE external request 3 event register */
	u8 res9[0x2];
	u16 ceexm3;		/* QE external request 3 mask register */
	u8 res10[0x2];
	u16 ceexe4;		/* QE external request 4 event register */
	u8 res11[0x2];
	u16 ceexm4;		/* QE external request 4 mask register */
	u8 res12[0x2];
	u8 res13[0x280];
} cp83xx_t;

/*
 * QE Multiplexer
 */

typedef struct qmx83xx {
	u32 cmxgcr;		/* CMX general clock route register */
	u32 cmxsi1cr_l;		/* CMX SI1 clock route low register */
	u32 cmxsi1cr_h;		/* CMX SI1 clock route high register */
	u32 cmxsi1syr;		/* CMX SI1 SYNC route register */
	u32 cmxucr1;		/* CMX UCC1, UCC3 clock route register */
	u32 cmxucr2;		/* CMX UCC5, UCC7 clock route register */
	u32 cmxucr3;		/* CMX UCC2, UCC4 clock route register */
	u32 cmxucr4;		/* CMX UCC6, UCC8 clock route register */
	u32 cmxupcr;		/* CMX UPC clock route register */
	u8 res0[0x1C];
} qmx83xx_t;

/*
* QE Timers
*/

typedef struct qet83xx {
	u8 gtcfr1;		/* Timer 1 and Timer 2 global configuration register */
	u8 res0[0x3];
	u8 gtcfr2;		/* Timer 3 and timer 4 global configuration register */
	u8 res1[0xB];
	u16 gtmdr1;		/* Timer 1 mode register */
	u16 gtmdr2;		/* Timer 2 mode register */
	u16 gtrfr1;		/* Timer 1 reference register */
	u16 gtrfr2;		/* Timer 2 reference register */
	u16 gtcpr1;		/* Timer 1 capture register */
	u16 gtcpr2;		/* Timer 2 capture register */
	u16 gtcnr1;		/* Timer 1 counter */
	u16 gtcnr2;		/* Timer 2 counter */
	u16 gtmdr3;		/* Timer 3 mode register */
	u16 gtmdr4;		/* Timer 4 mode register */
	u16 gtrfr3;		/* Timer 3 reference register */
	u16 gtrfr4;		/* Timer 4 reference register */
	u16 gtcpr3;		/* Timer 3 capture register */
	u16 gtcpr4;		/* Timer 4 capture register */
	u16 gtcnr3;		/* Timer 3 counter */
	u16 gtcnr4;		/* Timer 4 counter */
	u16 gtevr1;		/* Timer 1 event register */
	u16 gtevr2;		/* Timer 2 event register */
	u16 gtevr3;		/* Timer 3 event register */
	u16 gtevr4;		/* Timer 4 event register */
	u16 gtps;		/* Timer 1 prescale register */
	u8 res2[0x46];
} qet83xx_t;

/*
* spi
*/

typedef struct spi83xx {
	u8 res0[0x20];
	u32 spmode;		/* SPI mode register */
	u8 res1[0x2];
	u8 spie;		/* SPI event register */
	u8 res2[0x1];
	u8 res3[0x2];
	u8 spim;		/* SPI mask register */
	u8 res4[0x1];
	u8 res5[0x1];
	u8 spcom;		/* SPI command register	 */
	u8 res6[0x2];
	u32 spitd;		/* SPI transmit data register (cpu mode) */
	u32 spird;		/* SPI receive data register (cpu mode) */
	u8 res7[0x8];
} spi83xx_t;

/*
* mcc
*/

typedef struct mcc83xx {
	u32 mcce;		/* MCC event register */
	u32 mccm;		/* MCC mask register */
	u32 mccf;		/* MCC configuration register */
	u32 merl;		/* MCC emergency request level register */
	u8 res0[0xF0];
} mcc83xx_t;

/*
* brg
*/

typedef struct brg83xx {
	u32 brgc1;		/* BRG1 configuration register */
	u32 brgc2;		/* BRG2 configuration register */
	u32 brgc3;		/* BRG3 configuration register */
	u32 brgc4;		/* BRG4 configuration register */
	u32 brgc5;		/* BRG5 configuration register */
	u32 brgc6;		/* BRG6 configuration register */
	u32 brgc7;		/* BRG7 configuration register */
	u32 brgc8;		/* BRG8 configuration register */
	u32 brgc9;		/* BRG9 configuration register */
	u32 brgc10;		/* BRG10 configuration register */
	u32 brgc11;		/* BRG11 configuration register */
	u32 brgc12;		/* BRG12 configuration register */
	u32 brgc13;		/* BRG13 configuration register */
	u32 brgc14;		/* BRG14 configuration register */
	u32 brgc15;		/* BRG15 configuration register */
	u32 brgc16;		/* BRG16 configuration register */
	u8 res0[0x40];
} brg83xx_t;

/*
* USB
*/

typedef struct usb83xx {
	u8 usmod;		/* USB mode register */
	u8 usadd;		/* USB address register */
	u8 uscom;		/* USB command register */
	u8 res0[0x1];
	u16 usep0;		/* USB endpoint register 0 */
	u16 usep1;		/* USB endpoint register 1 */
	u16 usep2;		/* USB endpoint register 2 */
	u16 usep3;		/* USB endpoint register 3 */
	u8 res1[0x4];
	u16 usber;		/* USB event register */
	u8 res2[0x2];
	u16 usbmr;		/* USB mask register */
	u8 res3[0x1];
	u8 usbs;		/* USB status register */
	u32 ussft;		/* USB start of frame timer */
	u8 res4[0x24];
} usb83xx_t;

/*
* SI
*/

typedef struct si1_83xx {
	u16 siamr1;		/* SI1 TDMA mode register */
	u16 sibmr1;		/* SI1 TDMB mode register */
	u16 sicmr1;		/* SI1 TDMC mode register */
	u16 sidmr1;		/* SI1 TDMD mode register */
	u8 siglmr1_h;		/* SI1 global mode register high */
	u8 res0[0x1];
	u8 sicmdr1_h;		/* SI1 command register high */
	u8 res2[0x1];
	u8 sistr1_h;		/* SI1 status register high */
	u8 res3[0x1];
	u16 sirsr1_h;		/* SI1 RAM shadow address register high */
	u8 sitarc1;		/* SI1 RAM counter Tx TDMA */
	u8 sitbrc1;		/* SI1 RAM counter Tx TDMB */
	u8 sitcrc1;		/* SI1 RAM counter Tx TDMC */
	u8 sitdrc1;		/* SI1 RAM counter Tx TDMD */
	u8 sirarc1;		/* SI1 RAM counter Rx TDMA */
	u8 sirbrc1;		/* SI1 RAM counter Rx TDMB */
	u8 sircrc1;