immap_83xx.h

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#define CAPTURE_ECC_ECE_SHIFT			0
	u8 res6[0x14];
	u32 err_detect;		/**< Memory Error Detect */
#define ECC_ERROR_DETECT_MME			(0x80000000>>0) /* Multiple Memory Errors */
#define ECC_ERROR_DETECT_MBE			(0x80000000>>28)	/* Multiple-Bit Error */
#define ECC_ERROR_DETECT_SBE			(0x80000000>>29)	/* Single-Bit ECC Error Pickup */
#define ECC_ERROR_DETECT_MSE			(0x80000000>>31)	/* Memory Select Error */
	u32 err_disable;	/**< Memory Error Disable */
#define ECC_ERROR_DISABLE_MBED			(0x80000000>>28)	/* Multiple-Bit ECC Error Disable */
#define ECC_ERROR_DISABLE_SBED			(0x80000000>>29)	/* Sinle-Bit ECC Error disable */
#define ECC_ERROR_DISABLE_MSED			(0x80000000>>31)	/* Memory Select Error Disable */
#define ECC_ERROR_ENABLE			~(ECC_ERROR_DISABLE_MSED|ECC_ERROR_DISABLE_SBED|ECC_ERROR_DISABLE_MBED)
	u32 err_int_en;		/**< Memory Error Interrupt Enable */
#define ECC_ERR_INT_EN_MBEE			(0x80000000>>28)	/* Multiple-Bit ECC Error Interrupt Enable */
#define ECC_ERR_INT_EN_SBEE			(0x80000000>>29)	/* Single-Bit ECC Error Interrupt Enable */
#define ECC_ERR_INT_EN_MSEE			(0x80000000>>31)	/* Memory Select Error Interrupt Enable */
#define ECC_ERR_INT_DISABLE			~(ECC_ERR_INT_EN_MBEE|ECC_ERR_INT_EN_SBEE|ECC_ERR_INT_EN_MSEE)
	u32 capture_attributes; /**< Memory Error Attributes Capture */
#define ECC_CAPT_ATTR_BNUM			(0xe0000000>>1) /* Data Beat Num */
#define ECC_CAPT_ATTR_BNUM_SHIFT		28
#define ECC_CAPT_ATTR_TSIZ			(0xc0000000>>6) /* Transaction Size */
#define ECC_CAPT_ATTR_TSIZ_FOUR_DW		0
#define ECC_CAPT_ATTR_TSIZ_ONE_DW		1
#define ECC_CAPT_ATTR_TSIZ_TWO_DW		2
#define ECC_CAPT_ATTR_TSIZ_THREE_DW		3
#define ECC_CAPT_ATTR_TSIZ_SHIFT		24
#define ECC_CAPT_ATTR_TSRC			(0xf8000000>>11)	/* Transaction Source */
#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT		0x0
#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF		0x2
#define ECC_CAPT_ATTR_TSRC_TSEC1		0x4
#define ECC_CAPT_ATTR_TSRC_TSEC2		0x5
#define ECC_CAPT_ATTR_TSRC_USB			(0x06|0x07)
#define ECC_CAPT_ATTR_TSRC_ENCRYPT		0x8
#define ECC_CAPT_ATTR_TSRC_I2C			0x9
#define ECC_CAPT_ATTR_TSRC_JTAG			0xA
#define ECC_CAPT_ATTR_TSRC_PCI1			0xD
#define ECC_CAPT_ATTR_TSRC_PCI2			0xE
#define ECC_CAPT_ATTR_TSRC_DMA			0xF
#define ECC_CAPT_ATTR_TSRC_SHIFT		16
#define ECC_CAPT_ATTR_TTYP			(0xe0000000>>18)	/* Transaction Type */
#define ECC_CAPT_ATTR_TTYP_WRITE		0x1
#define ECC_CAPT_ATTR_TTYP_READ			0x2
#define ECC_CAPT_ATTR_TTYP_R_M_W		0x3
#define ECC_CAPT_ATTR_TTYP_SHIFT		12
#define ECC_CAPT_ATTR_VLD			(0x80000000>>31)	/* Valid */
	u32 capture_address;	/**< Memory Error Address Capture */
	u32 capture_ext_address;/**< Memory Error Extended Address Capture */
	u32 err_sbe;		/**< Memory Single-Bit ECC Error Management */
#define ECC_ERROR_MAN_SBET			(0xff000000>>8) /* Single-Bit Error Threshold 0..255 */
#define ECC_ERROR_MAN_SBET_SHIFT		16
#define ECC_ERROR_MAN_SBEC			(0xff000000>>24)	/* Single Bit Error Counter 0..255 */
#define ECC_ERROR_MAN_SBEC_SHIFT		0
	u8 res7[0xA4];
	u32 debug_reg;
	u8 res8[0xFC];
} ddr83xx_t;

/*
 * I2C1 Controller
 */

/*
 * DUART
 */
typedef struct duart83xx {
	u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */
	u8 uier_udmb;	   /**< combined register for UIER and UDMB */
	u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */
	u8 ulcr;	/**< line control register */
	u8 umcr;	/**< MODEM control register */
	u8 ulsr;	/**< line status register */
	u8 umsr;	/**< MODEM status register */
	u8 uscr;	/**< scratch register */
	u8 res0[8];
	u8 udsr;	/**< DMA status register */
	u8 res1[3];
	u8 res2[0xEC];
} duart83xx_t;

/*
 * Local Bus Controller Registers
 */
typedef struct lbus_bank {
	u32 br;		    /**< Base Register	*/
	u32 or;		    /**< Base Register	*/
} lbus_bank_t;

typedef struct lbus83xx {
	lbus_bank_t bank[8];
	u8 res0[0x28];
	u32 mar;		/**< UPM Address Register */
	u8 res1[0x4];
	u32 mamr;		/**< UPMA Mode Register */
	u32 mbmr;		/**< UPMB Mode Register */
	u32 mcmr;		/**< UPMC Mode Register */
	u8 res2[0x8];
	u32 mrtpr;		/**< Memory Refresh Timer Prescaler Register */
	u32 mdr;		/**< UPM Data Register */
	u8 res3[0x8];
	u32 lsdmr;		/**< SDRAM Mode Register */
	u8 res4[0x8];
	u32 lurt;		/**< UPM Refresh Timer */
	u32 lsrt;		/**< SDRAM Refresh Timer */
	u8 res5[0x8];
	u32 ltesr;		/**< Transfer Error Status Register */
	u32 ltedr;		/**< Transfer Error Disable Register */
	u32 lteir;		/**< Transfer Error Interrupt Register */
	u32 lteatr;		/**< Transfer Error Attributes Register */
	u32 ltear;		/**< Transfer Error Address Register */
	u8 res6[0xC];
	u32 lbcr;		/**< Configuration Register */
#define LBCR_LDIS  0x80000000
#define LBCR_LDIS_SHIFT	   31
#define LBCR_BCTLC 0x00C00000
#define LBCR_BCTLC_SHIFT   22
#define LBCR_LPBSE 0x00020000
#define LBCR_LPBSE_SHIFT   17
#define LBCR_EPAR  0x00010000
#define LBCR_EPAR_SHIFT	   16
#define LBCR_BMT   0x0000FF00
#define LBCR_BMT_SHIFT	    8
	u32 lcrr;		/**< Clock Ratio Register */
#define LCRR_DBYP    0x80000000
#define LCRR_DBYP_SHIFT	     31
#define LCRR_BUFCMDC 0x30000000
#define LCRR_BUFCMDC_SHIFT   28
#define LCRR_ECL     0x03000000
#define LCRR_ECL_SHIFT	     24
#define LCRR_EADC    0x00030000
#define LCRR_EADC_SHIFT	     16
#define LCRR_CLKDIV  0x0000000F
#define LCRR_CLKDIV_SHIFT     0

	u8 res7[0x28];
	u8 res8[0xF00];
} lbus83xx_t;

#if defined (CONFIG_MPC8349)
/*
 * Serial Peripheral Interface
 */
typedef struct spi83xx {
	u32 mode;     /**< mode register  */
	u32 event;    /**< event register */
	u32 mask;     /**< mask register  */
	u32 com;      /**< command register */
	u8 res0[0x10];
	u32 tx;	      /**< transmit register */
	u32 rx;	      /**< receive register */
	u8 res1[0xD8];
} spi83xx_t;
#endif

/*
 * DMA/Messaging Unit
 */
typedef struct dma83xx {
	u32 res0[0xC];		/* 0x0-0x29 reseverd */
	u32 omisr;		/* 0x30 Outbound message interrupt status register */
	u32 omimr;		/* 0x34 Outbound message interrupt mask register */
	u32 res1[0x6];		/* 0x38-0x49 reserved */

	u32 imr0;		/* 0x50 Inbound message register 0 */
	u32 imr1;		/* 0x54 Inbound message register 1 */
	u32 omr0;		/* 0x58 Outbound message register 0 */
	u32 omr1;		/* 0x5C Outbound message register 1 */

	u32 odr;		/* 0x60 Outbound doorbell register */
	u32 res2;		/* 0x64-0x67 reserved */
	u32 idr;		/* 0x68 Inbound doorbell register */
	u32 res3[0x5];		/* 0x6C-0x79 reserved */

	u32 imisr;		/* 0x80 Inbound message interrupt status register */
	u32 imimr;		/* 0x84 Inbound message interrupt mask register */
	u32 res4[0x1E];		/* 0x88-0x99 reserved */

	u32 dmamr0;		/* 0x100 DMA 0 mode register */
	u32 dmasr0;		/* 0x104 DMA 0 status register */
	u32 dmacdar0;		/* 0x108 DMA 0 current descriptor address register */
	u32 res5;		/* 0x10C reserved */
	u32 dmasar0;		/* 0x110 DMA 0 source address register */
	u32 res6;		/* 0x114 reserved */
	u32 dmadar0;		/* 0x118 DMA 0 destination address register */
	u32 res7;		/* 0x11C reserved */
	u32 dmabcr0;		/* 0x120 DMA 0 byte count register */
	u32 dmandar0;		/* 0x124 DMA 0 next descriptor address register */
	u32 res8[0x16];		/* 0x128-0x179 reserved */

	u32 dmamr1;		/* 0x180 DMA 1 mode register */
	u32 dmasr1;		/* 0x184 DMA 1 status register */
	u32 dmacdar1;		/* 0x188 DMA 1 current descriptor address register */
	u32 res9;		/* 0x18C reserved */
	u32 dmasar1;		/* 0x190 DMA 1 source address register */
	u32 res10;		/* 0x194 reserved */
	u32 dmadar1;		/* 0x198 DMA 1 destination address register */
	u32 res11;		/* 0x19C reserved */
	u32 dmabcr1;		/* 0x1A0 DMA 1 byte count register */
	u32 dmandar1;		/* 0x1A4 DMA 1 next descriptor address register */
	u32 res12[0x16];	/* 0x1A8-0x199 reserved */

	u32 dmamr2;		/* 0x200 DMA 2 mode register */
	u32 dmasr2;		/* 0x204 DMA 2 status register */
	u32 dmacdar2;		/* 0x208 DMA 2 current descriptor address register */
	u32 res13;		/* 0x20C reserved */
	u32 dmasar2;		/* 0x210 DMA 2 source address register */
	u32 res14;		/* 0x214 reserved */
	u32 dmadar2;		/* 0x218 DMA 2 destination address register */
	u32 res15;		/* 0x21C reserved */
	u32 dmabcr2;		/* 0x220 DMA 2 byte count register */
	u32 dmandar2;		/* 0x224 DMA 2 next descriptor address register */
	u32 res16[0x16];	/* 0x228-0x279 reserved */

	u32 dmamr3;		/* 0x280 DMA 3 mode register */
	u32 dmasr3;		/* 0x284 DMA 3 status register */
	u32 dmacdar3;		/* 0x288 DMA 3 current descriptor address register */
	u32 res17;		/* 0x28C reserved */
	u32 dmasar3;		/* 0x290 DMA 3 source address register */
	u32 res18;		/* 0x294 reserved */
	u32 dmadar3;		/* 0x298 DMA 3 destination address register */
	u32 res19;		/* 0x29C reserved */
	u32 dmabcr3;		/* 0x2A0 DMA 3 byte count register */
	u32 dmandar3;		/* 0x2A4 DMA 3 next descriptor address register */

	u32 dmagsr;		/* 0x2A8 DMA general status register */
	u32 res20[0x15];	/* 0x2AC-0x2FF reserved */
} dma83xx_t;

/* DMAMRn bits */
#define DMA_CHANNEL_START			(0x00000001)	/* Bit - DMAMRn CS */
#define DMA_CHANNEL_TRANSFER_MODE_DIRECT	(0x00000004)	/* Bit - DMAMRn CTM */
#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN	(0x00001000)	/* Bit - DMAMRn SAHE */
#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B	(0x00000000)	/* 2Bit- DMAMRn SAHTS 1byte */
#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B	(0x00004000)	/* 2Bit- DMAMRn SAHTS 2bytes */
#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B	(0x00008000)	/* 2Bit- DMAMRn SAHTS 4bytes */
#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B	(0x0000c000)	/* 2Bit- DMAMRn SAHTS 8bytes */
#define DMA_CHANNEL_SNOOP			(0x00010000)	/* Bit - DMAMRn DMSEN */

/* DMASRn bits */
#define DMA_CHANNEL_BUSY			(0x00000004)	/* Bit - DMASRn CB */
#define DMA_CHANNEL_TRANSFER_ERROR		(0x00000080)	/* Bit - DMASRn TE */

/*
 * PCI Software Configuration Registers
 */
typedef struct pciconf83xx {
	u32 config_address;
#define PCI_CONFIG_ADDRESS_EN	0x80000000
#define PCI_CONFIG_ADDRESS_BN_SHIFT	16
#define PCI_CONFIG_ADDRESS_BN_MASK	0x00ff0000
#define PCI_CONFIG_ADDRESS_DN_SHIFT	11
#define PCI_CONFIG_ADDRESS_DN_MASK	0x0000f800
#define PCI_CONFIG_ADDRESS_FN_SHIFT	8
#define PCI_CONFIG_ADDRESS_FN_MASK	0x00000700
#define PCI_CONFIG_ADDRESS_RN_SHIFT	0
#define PCI_CONFIG_ADDRESS_RN_MASK	0x000000fc
	u32 config_data;
	u32 int_ack;
	u8 res[116];
} pciconf83xx_t;

/*
 * PCI Outbound Translation Register
 */
typedef struct pci_outbound_window {
	u32 potar;
	u8 res0[4];
	u32 pobar;
	u8 res1[4];
	u32 pocmr;
	u8 res2[4];
} pot83xx_t;

/*
 * Sequencer
 */
typedef struct ios83xx {
	pot83xx_t pot[6];
#define POTAR_TA_MASK	0x000fffff
#define POBAR_BA_MASK	0x000fffff
#define POCMR_EN	0x80000000
#define POCMR_IO	0x40000000	/* 0--memory space 1--I/O space */
#define POCMR_SE	0x20000000	/* streaming enable */
#define POCMR_DST	0x10000000	/* 0--PCI1 1--PCI2 */
#define POCMR_CM_MASK	0x000fffff
#define POCMR_CM_4G	0x00000000
#define POCMR_CM_2G	0x00080000
#define POCMR_CM_1G	0x000C0000
#define POCMR_CM_512M	0x000E0000
#define POCMR_CM_256M	0x000F0000
#define POCMR_CM_128M	0x000F8000
#define POCMR_CM_64M	0x000FC000
#define POCMR_CM_32M	0x000FE000
#define POCMR_CM_16M	0x000FF000
#define POCMR_CM_8M	0x000FF800
#define POCMR_CM_4M	0x000FFC00
#define POCMR_CM_2M	0x000FFE00
#define POCMR_CM_1M	0x000FFF00
#define POCMR_CM_512K	0x000FFF80
#define POCMR_CM_256K	0x000FFFC0
#define POCMR_CM_128K	0x000FFFE0
#define POCMR_CM_64K	0x000FFFF0
#define POCMR_CM_32K	0x000FFFF8
#define POCMR_CM_16K	0x000FFFFC
#define POCMR_CM_8K	0x000FFFFE
#define POCMR_CM_4K	0x000FFFFF
	u8 res0[0x60];
	u32 pmcr;
	u8 res1[4];
	u32 dtcr;
	u8 res2[4];
} ios83xx_t;

/*
 * PCI Controller Control and Status Registers
 */
typedef struct pcictrl83xx {
	u32 esr;
#define ESR_MERR	0x80000000
#define ESR_APAR	0x00000400
#define ESR_PCISERR	0x00000200
#define ESR_MPERR	0x00000100
#define ESR_TPERR	0x00000080
#define ESR_NORSP	0x00000040
#define ESR_TABT	0x00000020
	u32 ecdr;
#define ECDR_APAR	0x00000400
#define ECDR_PCISERR	0x00000200
#define ECDR_MPERR	0x00000100
#define ECDR_TPERR	0x00000080
#define ECDR_NORSP	0x00000040
#define ECDR_TABT	0x00000020
	u32 eer;
#define EER_APAR	0x00000400
#define EER_PCISERR	0x00000200
#define EER_MPERR	0x00000100
#define EER_TPERR	0x00000080
#define EER_NORSP	0x00000040
#define EER_TABT	0x00000020
	u32 eatcr;
#define EATCR_ERRTYPR_MASK	0x70000000
#define EATCR_ERRTYPR_APR	0x00000000	/* address parity error */
#define EATCR_ERRTYPR_WDPR	0x10000000	/* write data parity error */
#define EATCR_ERRTYPR_RDPR	0x20000000	/* read data parity error */
#define EATCR_ERRTYPR_MA	0x30000000	/* master abort */
#define EATCR_ERRTYPR_TA	0x40000000	/* target abort */
#define EATCR_ERRTYPR_SE	0x50000000	/* system error indication received */