immap_83xx.h

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	u32 sccr;		/* system clock control Register  */
#if defined (CONFIG_MPC8349)
#define SCCR_TSEC1CM  0xc0000000	/* TSEC1CM  */
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC2CM  0x30000000	/* TSEC2CM  */
#define SCCR_TSEC2CM_SHIFT 28
#endif
#define SCCR_ENCCM    0x03000000	/* ENCCM  */
#define SCCR_ENCCM_SHIFT 24
#if defined (CONFIG_MPC8349)
#define SCCR_USBMPHCM 0x00c00000	/* USBMPHCM  */
#define SCCR_USBMPHCM_SHIFT 22
#define SCCR_USBDRCM  0x00300000	/* USBDRCM  */
#define SCCR_USBDRCM_SHIFT 20
#endif
#define SCCR_PCICM    0x00010000	/* PCICM  */
#if defined (CONFIG_MPC8349)
#define SCCR_RES	~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
			| SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM)
#endif
#if defined (CONFIG_MPC8360)
#define SCCR_RES	~(SCCR_ENCCM | SCCR_PCICM)
#endif
	u8 res0[0xF4];
} clk83xx_t;

/*
 * Power Management Control Module
 */
typedef struct pmc83xx {
	u32 pmccr;		/* PMC Configuration Register  */
#define PMCCR_SLPEN 0x00000001	/* System Low Power Enable  */
#define PMCCR_DLPEN 0x00000002	/* DDR SDRAM Low Power Enable  */
#if defined (CONFIG_MPC8360)
#define PMCCR_SDLPEN 0x00000004 /* Secondary DDR SDRAM Low Power Enable	 */
#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN | PMCCR_SDLPEN)
#elif defined (CONFIG_MPC8349)
#define PMCCR_RES    ~(PMCCR_SLPEN | PMCCR_DLPEN)
#endif
	u32 pmcer;		/* PMC Event Register  */
#define PMCER_PMCI  0x00000001	/* PMC Interrupt  */
#define PMCER_RES ~(PMCER_PMCI)
	u32 pmcmr;		/* PMC Mask Register  */
#define PMCMR_PMCIE 0x0001	/* PMC Interrupt Enable	 */
#define PMCMR_RES ~(PMCMR_PMCIE)
	u8 res0[0xF4];
} pmc83xx_t;

#if defined (CONFIG_MPC8349)
/*
 * general purpose I/O module
 */
typedef struct gpio83xx {
	u32 dir;		/* direction register */
	u32 odr;		/* open drain register */
	u32 dat;		/* data register */
	u32 ier;		/* interrupt event register */
	u32 imr;		/* interrupt mask register */
	u32 icr;		/* external interrupt control register */
	u8 res0[0xE8];
} gpio83xx_t;
#endif

#if defined (CONFIG_MPC8360)
/*
 * QE Ports Interrupts Registers
 */
typedef struct qepi83xx {
	u8 res0[0xC];
	u32 qepier;		/* QE Ports Interrupt Event Register */
#define QEPIER_PA15 0x80000000
#define QEPIER_PA16 0x40000000
#define QEPIER_PA29 0x20000000
#define QEPIER_PA30 0x10000000
#define QEPIER_PB3  0x08000000
#define QEPIER_PB5  0x04000000
#define QEPIER_PB12 0x02000000
#define QEPIER_PB13 0x01000000
#define QEPIER_PB26 0x00800000
#define QEPIER_PB27 0x00400000
#define QEPIER_PC27 0x00200000
#define QEPIER_PC28 0x00100000
#define QEPIER_PC29 0x00080000
#define QEPIER_PD12 0x00040000
#define QEPIER_PD13 0x00020000
#define QEPIER_PD16 0x00010000
#define QEPIER_PD17 0x00008000
#define QEPIER_PD26 0x00004000
#define QEPIER_PD27 0x00002000
#define QEPIER_PE12 0x00001000
#define QEPIER_PE13 0x00000800
#define QEPIER_PE24 0x00000400
#define QEPIER_PE25 0x00000200
#define QEPIER_PE26 0x00000100
#define QEPIER_PE27 0x00000080
#define QEPIER_PE31 0x00000040
#define QEPIER_PF20 0x00000020
#define QEPIER_PG31 0x00000010
#define QEPIER_RES ~(QEPIER_PA15|QEPIER_PA16|QEPIER_PA29|QEPIER_PA30|QEPIER_PB3 \
		   |QEPIER_PB5|QEPIER_PB12|QEPIER_PB13|QEPIER_PB26|QEPIER_PB27 \
		   |QEPIER_PC27|QEPIER_PC28|QEPIER_PC29|QEPIER_PD12|QEPIER_PD13 \
		   |QEPIER_PD16|QEPIER_PD17|QEPIER_PD26|QEPIER_PD27|QEPIER_PE12 \
		   |QEPIER_PE13|QEPIER_PE24|QEPIER_PE25|QEPIER_PE26|QEPIER_PE27 \
		   |QEPIER_PE31|QEPIER_PF20|QEPIER_PG31)
	u32 qepimr;		/* QE Ports Interrupt Mask Register */
#define QEPIMR_PA15 0x80000000
#define QEPIMR_PA16 0x40000000
#define QEPIMR_PA29 0x20000000
#define QEPIMR_PA30 0x10000000
#define QEPIMR_PB3  0x08000000
#define QEPIMR_PB5  0x04000000
#define QEPIMR_PB12 0x02000000
#define QEPIMR_PB13 0x01000000
#define QEPIMR_PB26 0x00800000
#define QEPIMR_PB27 0x00400000
#define QEPIMR_PC27 0x00200000
#define QEPIMR_PC28 0x00100000
#define QEPIMR_PC29 0x00080000
#define QEPIMR_PD12 0x00040000
#define QEPIMR_PD13 0x00020000
#define QEPIMR_PD16 0x00010000
#define QEPIMR_PD17 0x00008000
#define QEPIMR_PD26 0x00004000
#define QEPIMR_PD27 0x00002000
#define QEPIMR_PE12 0x00001000
#define QEPIMR_PE13 0x00000800
#define QEPIMR_PE24 0x00000400
#define QEPIMR_PE25 0x00000200
#define QEPIMR_PE26 0x00000100
#define QEPIMR_PE27 0x00000080
#define QEPIMR_PE31 0x00000040
#define QEPIMR_PF20 0x00000020
#define QEPIMR_PG31 0x00000010
#define QEPIMR_RES ~(QEPIMR_PA15|QEPIMR_PA16|QEPIMR_PA29|QEPIMR_PA30|QEPIMR_PB3 \
		   |QEPIMR_PB5|QEPIMR_PB12|QEPIMR_PB13|QEPIMR_PB26|QEPIMR_PB27 \
		   |QEPIMR_PC27|QEPIMR_PC28|QEPIMR_PC29|QEPIMR_PD12|QEPIMR_PD13 \
		   |QEPIMR_PD16|QEPIMR_PD17|QEPIMR_PD26|QEPIMR_PD27|QEPIMR_PE12 \
		   |QEPIMR_PE13|QEPIMR_PE24|QEPIMR_PE25|QEPIMR_PE26|QEPIMR_PE27 \
		   |QEPIMR_PE31|QEPIMR_PF20|QEPIMR_PG31)
	u32 qepicr;		/* QE Ports Interrupt Control Register */
#define QEPICR_PA15 0x80000000
#define QEPICR_PA16 0x40000000
#define QEPICR_PA29 0x20000000
#define QEPICR_PA30 0x10000000
#define QEPICR_PB3  0x08000000
#define QEPICR_PB5  0x04000000
#define QEPICR_PB12 0x02000000
#define QEPICR_PB13 0x01000000
#define QEPICR_PB26 0x00800000
#define QEPICR_PB27 0x00400000
#define QEPICR_PC27 0x00200000
#define QEPICR_PC28 0x00100000
#define QEPICR_PC29 0x00080000
#define QEPICR_PD12 0x00040000
#define QEPICR_PD13 0x00020000
#define QEPICR_PD16 0x00010000
#define QEPICR_PD17 0x00008000
#define QEPICR_PD26 0x00004000
#define QEPICR_PD27 0x00002000
#define QEPICR_PE12 0x00001000
#define QEPICR_PE13 0x00000800
#define QEPICR_PE24 0x00000400
#define QEPICR_PE25 0x00000200
#define QEPICR_PE26 0x00000100
#define QEPICR_PE27 0x00000080
#define QEPICR_PE31 0x00000040
#define QEPICR_PF20 0x00000020
#define QEPICR_PG31 0x00000010
#define QEPICR_RES ~(QEPICR_PA15|QEPICR_PA16|QEPICR_PA29|QEPICR_PA30|QEPICR_PB3 \
		   |QEPICR_PB5|QEPICR_PB12|QEPICR_PB13|QEPICR_PB26|QEPICR_PB27 \
		   |QEPICR_PC27|QEPICR_PC28|QEPICR_PC29|QEPICR_PD12|QEPICR_PD13 \
		   |QEPICR_PD16|QEPICR_PD17|QEPICR_PD26|QEPICR_PD27|QEPICR_PE12 \
		   |QEPICR_PE13|QEPICR_PE24|QEPICR_PE25|QEPICR_PE26|QEPICR_PE27 \
		   |QEPICR_PE31|QEPICR_PF20|QEPICR_PG31)
	u8 res1[0xE8];
} qepi83xx_t;

/*
 * general purpose I/O module
 */
typedef struct gpio_n {
	u32 podr;		/* Open Drain Register */
	u32 pdat;		/* Data Register */
	u32 dir1;		/* direction register 1 */
	u32 dir2;		/* direction register 2 */
	u32 ppar1;		/* Pin Assignment Register 1 */
	u32 ppar2;		/* Pin Assignment Register 2 */
} gpio_n_t;

typedef struct gpio83xx {
	gpio_n_t ioport[0x7];
	u8 res0[0x358];
} gpio83xx_t;

/*
 * QE Secondary Bus Access Windows
 */

typedef struct qesba83xx {
	u32 lbmcsar;		/* Local bus memory controller start address */
#define LBMCSAR_SA	0x000FFFFF	/* 20 most-significant bits of the start address */
#define LBMCSAR_RES	~(LBMCSAR_SA)
	u32 sdmcsar;		/* Secondary DDR memory controller start address */
#define SDMCSAR_SA	0x000FFFFF	/* 20 most-significant bits of the start address */
#define SDMCSAR_RES	~(SDMCSAR_SA)
	u8 res0[0x38];
	u32 lbmcear;		/* Local bus memory controller end address */
#define LBMCEAR_EA	0x000FFFFF	/* 20 most-significant bits of the end address */
#define LBMCEAR_RES	~(LBMCEAR_EA)
	u32 sdmcear;		/* Secondary DDR memory controller end address */
#define SDMCEAR_EA	0x000FFFFF	/* 20 most-significant bits of the end address */
#define SDMCEAR_RES	~(SDMCEAR_EA)
	u8 res1[0x38];
	u32 lbmcar;		/* Local bus memory controller attributes  */
#define LBMCAR_WEN	0x00000001	/* Forward transactions to the QE local bus */
#define LBMCAR_RES	~(LBMCAR_WEN)
	u32 sdmcar;		/* Secondary DDR memory controller attributes */
#define SDMCAR_WEN	0x00000001	/* Forward transactions to the second DDR bus */
#define SDMCAR_RES	~(SDMCAR_WEN)
	u8 res2[0x778];
} qesba83xx_t;
#endif

/*
 * DDR Memory Controller Memory Map
 */
typedef struct ddr_cs_bnds {
	u32 csbnds;
#define CSBNDS_SA 0x00FF0000
#define CSBNDS_SA_SHIFT	   8
#define CSBNDS_EA 0x000000FF
#define CSBNDS_EA_SHIFT	  24
	u8 res0[4];
} ddr_cs_bnds_t;

typedef struct ddr83xx {
	ddr_cs_bnds_t csbnds[4];	    /**< Chip Select x Memory Bounds */
	u8 res0[0x60];
	u32 cs_config[4];	/**< Chip Select x Configuration */
#define CSCONFIG_EN	    0x80000000
#define CSCONFIG_AP	    0x00800000
#define CSCONFIG_ROW_BIT    0x00000700
#define CSCONFIG_ROW_BIT_12 0x00000000
#define CSCONFIG_ROW_BIT_13 0x00000100
#define CSCONFIG_ROW_BIT_14 0x00000200
#define CSCONFIG_COL_BIT    0x00000007
#define CSCONFIG_COL_BIT_8  0x00000000
#define CSCONFIG_COL_BIT_9  0x00000001
#define CSCONFIG_COL_BIT_10 0x00000002
#define CSCONFIG_COL_BIT_11 0x00000003
	u8 res1[0x78];
	u32 timing_cfg_1;	/**< SDRAM Timing Configuration 1 */
#define TIMING_CFG1_PRETOACT 0x70000000
#define TIMING_CFG1_PRETOACT_SHIFT   28
#define TIMING_CFG1_ACTTOPRE 0x0F000000
#define TIMING_CFG1_ACTTOPRE_SHIFT   24
#define TIMING_CFG1_ACTTORW  0x00700000
#define TIMING_CFG1_ACTTORW_SHIFT    20
#define TIMING_CFG1_CASLAT   0x00070000
#define TIMING_CFG1_CASLAT_SHIFT     16
#define TIMING_CFG1_REFREC   0x0000F000
#define TIMING_CFG1_REFREC_SHIFT     12
#define TIMING_CFG1_WRREC    0x00000700
#define TIMING_CFG1_WRREC_SHIFT	      8
#define TIMING_CFG1_ACTTOACT 0x00000070
#define TIMING_CFG1_ACTTOACT_SHIFT    4
#define TIMING_CFG1_WRTORD   0x00000007
#define TIMING_CFG1_WRTORD_SHIFT      0
#define TIMING_CFG1_CASLAT_20 0x00030000	/* CAS latency = 2.0 */
#define TIMING_CFG1_CASLAT_25 0x00040000	/* CAS latency = 2.5 */

	u32 timing_cfg_2;	/**< SDRAM Timing Configuration 2 */
#define TIMING_CFG2_CPO		  0x0F000000
#define TIMING_CFG2_CPO_SHIFT		  24
#define TIMING_CFG2_ACSM	  0x00080000
#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
#define TIMING_CFG2_WR_DATA_DELAY_SHIFT	  10
#define TIMING_CFG2_CPO_DEF	  0x00000000	/* default (= CASLAT + 1) */

	u32 sdram_cfg;		/**< SDRAM Control Configuration */
#define SDRAM_CFG_MEM_EN     0x80000000
#define SDRAM_CFG_SREN	     0x40000000
#define SDRAM_CFG_ECC_EN     0x20000000
#define SDRAM_CFG_RD_EN	     0x10000000
#define SDRAM_CFG_SDRAM_TYPE 0x03000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT   24
#define SDRAM_CFG_DYN_PWR    0x00200000
#define SDRAM_CFG_32_BE	     0x00080000
#define SDRAM_CFG_8_BE	     0x00040000
#define SDRAM_CFG_NCAP	     0x00020000
#define SDRAM_CFG_2T_EN	     0x00008000
#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000

	u8 res2[4];
	u32 sdram_mode;		/**< SDRAM Mode Configuration */
#define SDRAM_MODE_ESD 0xFFFF0000
#define SDRAM_MODE_ESD_SHIFT   16
#define SDRAM_MODE_SD  0x0000FFFF
#define SDRAM_MODE_SD_SHIFT	0
#define DDR_MODE_EXT_MODEREG	0x4000	/* select extended mode reg */
#define DDR_MODE_EXT_OPMODE	0x3FF8	/* operating mode, mask */
#define DDR_MODE_EXT_OP_NORMAL	0x0000	/* normal operation */
#define DDR_MODE_QFC		0x0004	/* QFC / compatibility, mask */
#define DDR_MODE_QFC_COMP	0x0000	/* compatible to older SDRAMs */
#define DDR_MODE_WEAK		0x0002	/* weak drivers */
#define DDR_MODE_DLL_DIS	0x0001	/* disable DLL */
#define DDR_MODE_CASLAT		0x0070	/* CAS latency, mask */
#define DDR_MODE_CASLAT_15	0x0010	/* CAS latency 1.5 */
#define DDR_MODE_CASLAT_20	0x0020	/* CAS latency 2 */
#define DDR_MODE_CASLAT_25	0x0060	/* CAS latency 2.5 */
#define DDR_MODE_CASLAT_30	0x0030	/* CAS latency 3 */
#define DDR_MODE_BTYPE_SEQ	0x0000	/* sequential burst */
#define DDR_MODE_BTYPE_ILVD	0x0008	/* interleaved burst */
#define DDR_MODE_BLEN_2		0x0001	/* burst length 2 */
#define DDR_MODE_BLEN_4		0x0002	/* burst length 4 */
#define DDR_REFINT_166MHZ_7US	1302	/* exact value for 7.8125 µs */
#define DDR_BSTOPRE	256	/* use 256 cycles as a starting point */
#define DDR_MODE_MODEREG	0x0000	/* select mode register */

	u8 res3[8];
	u32 sdram_interval;	/**< SDRAM Interval Configuration */
#define SDRAM_INTERVAL_REFINT  0x3FFF0000
#define SDRAM_INTERVAL_REFINT_SHIFT    16
#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
#define SDRAM_INTERVAL_BSTOPRE_SHIFT	0
	u8 res9[8];
	u32 sdram_clk_cntl;
#define DDR_SDRAM_CLK_CNTL_SS_EN		0x80000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025	0x01000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05	0x02000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075	0x03000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1		0x04000000

	u8 res4[0xCCC];
	u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
	u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
	u32 ecc_err_inject;	/**< Memory Data Path Error Injection Mask ECC */
#define ECC_ERR_INJECT_EMB			(0x80000000>>22)	/* ECC Mirror Byte */
#define ECC_ERR_INJECT_EIEN			(0x80000000>>23)	/* Error Injection Enable */
#define ECC_ERR_INJECT_EEIM			(0xff000000>>24)	/* ECC Erroe Injection Enable */
#define ECC_ERR_INJECT_EEIM_SHIFT		0
	u8 res5[0x14];
	u32 capture_data_hi;	/**< Memory Data Path Read Capture High */
	u32 capture_data_lo;	/**< Memory Data Path Read Capture Low */
	u32 capture_ecc;	/**< Memory Data Path Read Capture ECC */
#define CAPTURE_ECC_ECE				(0xff000000>>24)