immap_83xx.h

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#endif
	u32 sipnr_l;		/*  System Internal Interrupt Pending Register - Low (SIPNR_L)	*/
#define SIIL_RTCS  0x80000000	/*  RTC SECOND interrupt  */
#define SIIL_PIT   0x40000000	/*  PIT interrupt  */
#define SIIL_PCI1  0x20000000	/*  PCI1 interrupt  */
#if defined (CONFIG_MPC8349)
#define SIIL_PCI2  0x10000000	/*  PCI2 interrupt  */
#endif
#define SIIL_RTCA  0x08000000	/*  RTC ALARM interrupt	 */
#define SIIL_MU	   0x04000000	/*  Message Unit interrupt  */
#define SIIL_SBA   0x02000000	/*  System Bus Arbiter interrupt  */
#define SIIL_DMA   0x01000000	/*  DMA interrupt  */
#define SIIL_GTM4  0x00800000	/*  GTM4 interrupt  */
#define SIIL_GTM8  0x00400000	/*  GTM8 interrupt  */
#if defined (CONFIG_MPC8349)
#define SIIL_GPIO1 0x00200000	/*  GPIO1 interrupt  */
#define SIIL_GPIO2 0x00100000	/*  GPIO2 interrupt  */
#endif
#if defined (CONFIG_MPC8360)
#define SIIL_QEP   0x00200000	/*  QE ports interrupt	*/
#define SIIL_SDDR  0x00100000	/*  SDDR interrupt  */
#endif
#define SIIL_DDR   0x00080000	/*  DDR interrupt  */
#define SIIL_LBC   0x00040000	/*  LBC interrupt  */
#define SIIL_GTM2  0x00020000	/*  GTM2 interrupt  */
#define SIIL_GTM6  0x00010000	/*  GTM6 interrupt  */
#define SIIL_PMC   0x00008000	/*  PMC interrupt  */
#define SIIL_GTM3  0x00000800	/*  GTM3 interrupt  */
#define SIIL_GTM7  0x00000400	/*  GTM7 interrupt  */
#define SIIL_GTM1  0x00000020	/*  GTM1 interrupt  */
#define SIIL_GTM5  0x00000010	/*  GTM5 interrupt  */
#define SIIL_DPTC  0x00000001	/*  DPTC interrupt (!!! Invisible for user !!!)	 */
#if defined (CONFIG_MPC8349)
#define SIIL_RES	~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \
			| SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \
			| SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \
			| SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \
			| SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \
			| SIIL_GTM5 |SIIL_DPTC )
#endif
#if defined (CONFIG_MPC8360)
#define SIIL_RES	~(SIIL_RTCS  |SIIL_PIT	|SIIL_PCI1 |SIIL_RTCALR \
			|SIIL_MU |SIIL_SBA  |SIIL_DMA  |SIIL_GTM4 |SIIL_GTM8 \
			|SIIL_QEP | SIIL_SDDR| SIIL_DDR	 |SIIL_LBC  |SIIL_GTM2 \
			|SIIL_GTM6 |SIIL_PMC  |SIIL_GTM3 |SIIL_GTM7 |SIIL_GTM1 \
			|SIIL_GTM5 )
#endif
	u32 siprr_a;		/*  System Internal Interrupt Group A Priority Register (PRR)  */
	u8 res0[8];
	u32 siprr_d;		/*  System Internal Interrupt Group D Priority Register (PRR)  */
	u32 simsr_h;		/*  System Internal Interrupt Mask Register - High (SIIH)  */
	u32 simsr_l;		/*  System Internal Interrupt Mask Register - Low (SIIL)  */
	u8 res1[4];
	u32 sepnr;		/*  System External Interrupt Pending Register (SEI)  */
	u32 smprr_a;		/*  System Mixed Interrupt Group A Priority Register (PRR)  */
	u32 smprr_b;		/*  System Mixed Interrupt Group B Priority Register (PRR)  */
#define PRR_0 0xe0000000	/* Priority Register, Position 0 programming */
#define PRR_1 0x1c000000	/* Priority Register, Position 1 programming */
#define PRR_2 0x03800000	/* Priority Register, Position 2 programming */
#define PRR_3 0x00700000	/* Priority Register, Position 3 programming */
#define PRR_4 0x0000e000	/* Priority Register, Position 4 programming */
#define PRR_5 0x00001c00	/* Priority Register, Position 5 programming */
#define PRR_6 0x00000380	/* Priority Register, Position 6 programming */
#define PRR_7 0x00000070	/* Priority Register, Position 7 programming */
#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7)
	u32 semsr;		/*  System External Interrupt Mask Register (SEI)  */
#define SEI_IRQ0  0x80000000	/*  IRQ0 external interrupt  */
#define SEI_IRQ1  0x40000000	/*  IRQ1 external interrupt  */
#define SEI_IRQ2  0x20000000	/*  IRQ2 external interrupt  */
#define SEI_IRQ3  0x10000000	/*  IRQ3 external interrupt  */
#define SEI_IRQ4  0x08000000	/*  IRQ4 external interrupt  */
#define SEI_IRQ5  0x04000000	/*  IRQ5 external interrupt  */
#define SEI_IRQ6  0x02000000	/*  IRQ6 external interrupt  */
#define SEI_IRQ7  0x01000000	/*  IRQ7 external interrupt  */
#define SEI_SIRQ0 0x00008000	/*  SIRQ0 external interrupt  */
#define SEI_RES		~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \
			| SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \
			| SEI_SIRQ0)
	u32 secnr;		/*  System External Interrupt Control Register (SECNR) */
#define SECNR_MIXB0T 0xc0000000 /*  MIXB0 priority position IPIC output interrupt type	*/
#define SECNR_MIXB1T 0x30000000 /*  MIXB1 priority position IPIC output interrupt type	*/
#define SECNR_MIXA0T 0x00c00000 /*  MIXA0 priority position IPIC output interrupt type	*/
#define SECNR_SYSA1T 0x00300000 /*  MIXA1 priority position IPIC output interrupt type	*/
#define SECNR_EDI0   0x00008000 /*  IRQ0 external interrupt edge/level detect  */
#define SECNR_EDI1   0x00004000 /*  IRQ1 external interrupt edge/level detect  */
#define SECNR_EDI2   0x00002000 /*  IRQ2 external interrupt edge/level detect  */
#define SECNR_EDI3   0x00001000 /*  IRQ3 external interrupt edge/level detect  */
#define SECNR_EDI4   0x00000800 /*  IRQ4 external interrupt edge/level detect  */
#define SECNR_EDI5   0x00000400 /*  IRQ5 external interrupt edge/level detect  */
#define SECNR_EDI6   0x00000200 /*  IRQ6 external interrupt edge/level detect  */
#define SECNR_EDI7   0x00000100 /*  IRQ7 external interrupt edge/level detect  */
#define SECNR_RES	~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \
			| SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \
			| SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \
			| SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7)
	u32 sersr;		/*  System Error Status Register (SERR)	 */
	u32 sermr;		/*  System Error Mask Register (SERR)  */
#define SERR_IRQ0 0x80000000	/*  IRQ0 MCP request  */
#define SERR_WDT  0x40000000	/*  WDT MCP request  */
#define SERR_SBA  0x20000000	/*  SBA MCP request  */
#if defined (CONFIG_MPC8349)
#define SERR_DDR  0x10000000	/*  DDR MCP request  */
#define SERR_LBC  0x08000000	/*  LBC MCP request  */
#define SERR_PCI1 0x04000000	/*  PCI1 MCP request  */
#define SERR_PCI2 0x02000000	/*  PCI2 MCP request  */
#endif
#if defined (CONFIG_MPC8360)
#define SERR_CIEE 0x10000000	/*  CIEE MCP request  */
#define SERR_CMEE 0x08000000	/*  CMEEMCP request  */
#define SERR_PCI  0x04000000	/*  PCI MCP request  */
#endif
#define SERR_MU	  0x01000000	/*  MU MCP request  */
#define SERR_RNC  0x00010000	/*  MU MCP request (!!! Non-visible for users !!!)  */
#if defined (CONFIG_MPC8349)
#define SERR_RES	~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \
			|SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \
			|SERR_RNC )
#elif defined (CONFIG_MPC8360)
#define SERR_RES	~( SERR_IRQ0|SERR_WDT |SERR_SBA |SERR_CIEE\
			|SERR_CMEE|SERR_PCI|SERR_MU)
#endif
	u32 sercr;		/*  System Error Control Register  (SERCR)  */
#define SERCR_MCPR 0x00000001	/*  MCP Route  */
#define SERCR_RES ~(SERCR_MCPR)
	u8 res2[4];
	u32 sifcr_h;		/*  System Internal Interrupt Force Register - High (SIIH)  */
	u32 sifcr_l;		/*  System Internal Interrupt Force Register - Low (SIIL)  */
	u32 sefcr;		/*  System External Interrupt Force Register (SEI)  */
	u32 serfr;		/*  System Error Force Register (SERR)	*/
	u32 scvcr;		/* System Critical Interrupt Vector Register */
#define SCVCR_CVECX	0xFC000000	/* Backward (MPC8260) compatible
					   critical interrupt vector. */
#define SCVCR_CVEC	0x0000007F	/* Critical interrupt vector */
#define SCVCR_RES	~(SCVCR_CVECX|SCVCR_CVEC)
	u32 smvcr;		/* System Management Interrupt Vector Register */
#define SMVCR_CVECX	0xFC000000	/* Backward (MPC8260) compatible
					   critical interrupt vector. */
#define SMVCR_CVEC	0x0000007F	/* Critical interrupt vector */
#define SMVCR_RES	~(SMVCR_CVECX|SMVCR_CVEC)
	u8 res3[0x98];
} ipic83xx_t;

/*
 * System Arbiter Registers
 */
typedef struct arbiter83xx {
	u32 acr;		/* Arbiter Configuration Register */
#define ACR_COREDIS    0x10000000	/* Core disable. */
#define ACR_COREDIS_SHIFT		(31-7)
#define ACR_PIPE_DEP   0x00070000	/* Pipeline depth (number of outstanding transactions). */
#define ACR_PIPE_DEP_SHIFT		(31-15)
#define ACR_PCI_RPTCNT 0x00007000	/* PCI repeat count. */
#define ACR_PCI_RPTCNT_SHIFT		(31-19)
#define ACR_RPTCNT     0x00000700	/* Repeat count. */
#define ACR_RPTCNT_SHIFT		(31-23)
#define ACR_APARK      0x00000030	/* Address parking. */
#define ACR_APARK_SHIFT			(31-27)
#define ACR_PARKM	   0x0000000F	/* Parking master. */
#define ACR_PARKM_SHIFT			(31-31)
#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM)
	u32 atr;		/* Arbiter Timers Register */
#define ATR_DTO 0x00FF0000	/* Data time out. */
#define ATR_ATO 0x000000FF	/* Address time out. */
#define ATR_RES ~(ATR_DTO|ATR_ATO)
	u8 res[4];
	u32 aer;		/* Arbiter Event Register (AE) */
	u32 aidr;		/* Arbiter Interrupt Definition Register (AE) */
	u32 amr;		/* Arbiter Mask Register (AE) */
	u32 aeatr;		/* Arbiter Event Attributes Register */
#define AEATR_EVENT   0x07000000	/* Event type. */
#define AEATR_MSTR_ID 0x001F0000	/* Master Id. */
#define AEATR_TBST    0x00000800	/* Transfer burst. */
#define AEATR_TSIZE   0x00000700	/* Transfer Size. */
#define AEATR_TTYPE	  0x0000001F	/* Transfer Type. */
#define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE)
	u32 aeadr;		/* Arbiter Event Address Register */
	u32 aerr;		/* Arbiter Event Response Register (AE) */
#define AE_ETEA 0x00000020	/* Transfer error. */
#define AE_RES_ 0x00000010	/* Reserved transfer type. */
#define AE_ECW	0x00000008	/* External control word transfer type. */
#define AE_AO	0x00000004	/* Address Only transfer type. */
#define AE_DTO	0x00000002	/* Data time out. */
#define AE_ATO	0x00000001	/* Address time out. */
#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO)
	u8 res1[0xDC];
} arbiter83xx_t;

/*
 * Reset Module
 */
typedef struct reset83xx {
	u32 rcwl;		/* RCWL Register  */
#define RCWL_LBIUCM  0x80000000 /* LBIUCM  */
#define RCWL_LBIUCM_SHIFT    31
#define RCWL_DDRCM   0x40000000 /* DDRCM  */
#define RCWL_DDRCM_SHIFT     30
#if defined (CONFIG_MPC8349)
#define RCWL_SVCOD   0x30000000 /* SVCOD  */
#endif
#define RCWL_SPMF    0x0f000000 /* SPMF	 */
#define RCWL_SPMF_SHIFT	     24
#define RCWL_COREPLL 0x007F0000 /* COREPLL  */
#define RCWL_COREPLL_SHIFT   16
#define RCWL_CEVCOD  0x000000C0 /* CEVCOD  */
#define RCWL_CEPDF   0x00000020 /* CEPDF  */
#define RCWL_CEPDF_SHIFT      5
#define RCWL_CEPMF   0x0000001F /* CEPMF  */
#define RCWL_CEPMF_SHIFT      0
#if defined (CONFIG_MPC8349)
#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
#elif defined (CONFIG_MPC8360)
#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SPMF|RCWL_COREPLL|RCWL_CEPDF|RCWL_CEPMF)
#endif
	u32 rcwh;		/* RCHL Register  */
#define RCWH_PCIHOST 0x80000000 /* PCIHOST  */
#define RCWH_PCIHOST_SHIFT   31
#if defined (CONFIG_MPC8349)
#define RCWH_PCI64   0x40000000 /* PCI64  */
#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB  */
#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB  */
#elif defined (CONFIG_MPC8360)
#define RCWH_PCIARB   0x20000000	/* PCI internal arbiter mode. */
#define RCWH_PCICKDRV 0x10000000	/* PCI clock output drive. */
#endif
#define RCWH_COREDIS 0x08000000 /* COREDIS  */
#define RCWH_BMS     0x04000000 /* BMS	*/
#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ  */
#define RCWH_SWEN    0x00800000 /* SWEN	 */
#define RCWH_ROMLOC  0x00700000 /* ROMLOC  */
#if defined (CONFIG_MPC8349)
#define RCWH_TSEC1M  0x0000c000 /* TSEC1M  */
#define RCWH_TSEC2M  0x00003000 /* TSEC2M  */
#define RCWH_TPR     0x00000100 /* TPR	*/
#elif defined (CONFIG_MPC8360)
#define RCWH_SDDRIOE  0x00000010	/* Secondary DDR IO Enable.  */
#endif
#define RCWH_TLE     0x00000008 /* TLE	*/
#define RCWH_LALE    0x00000004 /* LALE	 */
#if defined (CONFIG_MPC8349)
#define RCWH_RES	~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \
			| RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \
			| RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \
			| RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \
			| RCWH_TLE | RCWH_LALE)
#elif defined (CONFIG_MPC8360)
#define RCWH_RES	~(RCWH_PCIHOST|RCWH_PCIARB|RCWH_PCICKDRV \
			|RCWH_COREDIS|RCWH_BMS|RCWH_BOOTSEQ|RCWH_SWEN \
			|RCWH_SDDRIOE |RCWH_TLE)
#endif
	u8 res0[8];
	u32 rsr;		/* Reset status Register  */
#define RSR_RSTSRC 0xE0000000	/* Reset source	 */
#define RSR_RSTSRC_SHIFT   29
#define RSR_BSF	   0x00010000	/* Boot seq. fail  */
#define RSR_BSF_SHIFT	   16
#define RSR_SWSR   0x00002000	/* software soft reset	*/
#define RSR_SWSR_SHIFT	   13
#define RSR_SWHR   0x00001000	/* software hard reset	*/
#define RSR_SWHR_SHIFT	   12
#define RSR_JHRS   0x00000200	/* jtag hreset	*/
#define RSR_JHRS_SHIFT	    9
#define RSR_JSRS   0x00000100	/* jtag sreset status  */
#define RSR_JSRS_SHIFT	    8
#define RSR_CSHR   0x00000010	/* checkstop reset status  */
#define RSR_CSHR_SHIFT	    4
#define RSR_SWRS   0x00000008	/* software watchdog reset status  */
#define RSR_SWRS_SHIFT	    3
#define RSR_BMRS   0x00000004	/* bus monitop reset status  */
#define RSR_BMRS_SHIFT	    2
#define RSR_SRS	   0x00000002	/* soft reset status  */
#define RSR_SRS_SHIFT	    1
#define RSR_HRS	   0x00000001	/* hard reset status  */
#define RSR_HRS_SHIFT	    0
#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS)
	u32 rmr;		/* Reset mode Register	*/
#define RMR_CSRE   0x00000001	/* checkstop reset enable  */
#define RMR_CSRE_SHIFT	    0
#define RMR_RES ~(RMR_CSRE)
	u32 rpr;		/* Reset protection Register  */
	u32 rcr;		/* Reset Control Register  */
#define RCR_SWHR 0x00000002	/* software hard reset	*/
#define RCR_SWSR 0x00000001	/* software soft reset	*/
#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
	u32 rcer;		/* Reset Control Enable Register  */
#define RCER_CRE 0x00000001	/* software hard reset	*/
#define RCER_RES ~(RCER_CRE)
	u8 res1[0xDC];
} reset83xx_t;

typedef struct clk83xx {
	u32 spmr;		/* system PLL mode Register  */
#define SPMR_LBIUCM  0x80000000 /* LBIUCM  */
#define SPMR_DDRCM   0x40000000 /* DDRCM  */
#if defined (CONFIG_MPC8349)
#define SPMR_SVCOD   0x30000000 /* SVCOD  */
#endif
#define SPMR_SPMF    0x0F000000 /* SPMF	 */
#define SPMR_CKID    0x00800000 /* CKID	 */
#define SPMR_CKID_SHIFT 23
#define SPMR_COREPLL 0x007F0000 /* COREPLL  */
#define SPMR_CEVCOD  0x000000C0 /* CEVCOD  */
#define SPMR_CEPDF   0x00000020 /* CEPDF  */
#define SPMR_CEPMF   0x0000001F /* CEPMF  */
#if defined (CONFIG_MPC8349)
#define SPMR_RES	~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \
			| SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \
			| SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF)
#elif defined (CONFIG_MPC8360)
#define SPMR_RES	~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SPMF \
			| SPMR_CKID | SPMR_COREPLL | SPMR_CEVCOD \
			| SPMR_CEPDF | SPMR_CEPMF)
#endif
	u32 occr;		/* output clock control Register  */
#define OCCR_PCICOE0 0x80000000 /* PCICOE0  */
#define OCCR_PCICOE1 0x40000000 /* PCICOE1  */
#define OCCR_PCICOE2 0x20000000 /* PCICOE2  */
#if defined (CONFIG_MPC8349)
#define OCCR_PCICOE3 0x10000000 /* PCICOE3  */
#define OCCR_PCICOE4 0x08000000 /* PCICOE4  */
#define OCCR_PCICOE5 0x04000000 /* PCICOE5  */
#define OCCR_PCICOE6 0x02000000 /* PCICOE6  */
#define OCCR_PCICOE7 0x01000000 /* PCICOE7  */
#endif
#define OCCR_PCICD0  0x00800000 /* PCICD0  */
#define OCCR_PCICD1  0x00400000 /* PCICD1  */
#define OCCR_PCICD2  0x00200000 /* PCICD2  */
#if defined (CONFIG_MPC8349)
#define OCCR_PCICD3  0x00100000 /* PCICD3  */
#define OCCR_PCICD4  0x00080000 /* PCICD4  */
#define OCCR_PCICD5  0x00040000 /* PCICD5  */
#define OCCR_PCICD6  0x00020000 /* PCICD6  */
#define OCCR_PCICD7  0x00010000 /* PCICD7  */
#define OCCR_PCI1CR  0x00000002 /* PCI1CR  */
#define OCCR_PCI2CR  0x00000001 /* PCI2CR  */
#define OCCR_RES	~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \
			| OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \
			| OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \
			| OCCR_PCICD1 | OCCR_PCICD2  | OCCR_PCICD3 \
			| OCCR_PCICD4  | OCCR_PCICD5 | OCCR_PCICD6  \
			| OCCR_PCICD7  | OCCR_PCI1CR  | OCCR_PCI2CR )
#endif
#if defined (CONFIG_MPC8360)
#define OCCR_PCICR	0x00000002	/* PCI clock rate  */
#define OCCR_RES	~(OCCR_PCICOE0|OCCR_PCICOE1|OCCR_PCICOE2 \
			|OCCR_PCICD0|OCCR_PCICD1|OCCR_PCICD2|OCCR_PCICR )
#endif