immap_83xx.h

from [e-mail] 电路原理图和详细说明： amd.9966.org或者 arm.9966.org 都是原创,包括boot, loader,u-boot,linu

/*
 * (C) Copyright 2004-2006 Freescale Semiconductor, Inc.
 *
 * MPC83xx Internal Memory Map
 *
 * History :
 * 20060601: Daveliu ([e-mail])
 *	     TanyaJiang ([e-mail])
 *	     Unified variable names for mpc83xx
 * 2005	   : Mandy Lavi ([e-mail])
 *	     support for mpc8360e
 * 2004	   : Eran Liberty ([e-mail])
 *	     Initialized for mpc8349
 *	     based on:
 *	     MPC8260 Internal Memory Map
 *	     Copyright (c) 1999 Dan Malek ([e-mail])
 *	     MPC85xx Internal Memory Map
 *	     Copyright(c) 2002,2003 Motorola Inc.
 *	     Xianghua Xiao ([e-mail])
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */
#ifndef __IMMAP_83xx__
#define __IMMAP_83xx__

#include <config.h>
#include <asm/types.h>
#include <asm/fsl_i2c.h>

/*
 * Local Access Window.
 */
typedef struct law83xx {
	u32 bar;		/* LBIU local access window base address register */
/* Identifies the 20 most-significant address bits of the base of local
 * access window n. The specified base address should be aligned to the
 * window size, as defined by LBLAWARn[SIZE].
 */
#define LAWBAR_BAR	   0xFFFFF000
#define LAWBAR_RES	     ~(LAWBAR_BAR)
	u32 ar;			/* LBIU local access window attribute register */
} law83xx_t;

/*
 * System configuration registers.
 */
typedef struct sysconf83xx {
	u32 immrbar;		/* Internal memory map base address register */
	u8 res0[0x04];
	u32 altcbar;		/* Alternate configuration base address register */
/* Identifies the12 most significant address bits of an alternate base
 * address used for boot sequencer configuration accesses.
 */
#define ALTCBAR_BASE_ADDR     0xFFF00000
#define ALTCBAR_RES	      ~(ALTCBAR_BASE_ADDR)	/* Reserved. Write has no effect, read returns 0. */
	u8 res1[0x14];
	law83xx_t lblaw[4];	/* LBIU local access window */
	u8 res2[0x20];
	law83xx_t pcilaw[2];	/* PCI local access window */
	u8 res3[0x30];
	law83xx_t ddrlaw[2];	/* DDR local access window */
	u8 res4[0x50];
	u32 sgprl;		/* System General Purpose Register Low */
	u32 sgprh;		/* System General Purpose Register High */
	u32 spridr;		/* System Part and Revision ID Register */
#define SPRIDR_PARTID	      0xFFFF0000	/* Part Identification. */
#define SPRIDR_REVID	      0x0000FFFF	/* Revision Identification. */
	u8 res5[0x04];
	u32 spcr;		/* System Priority Configuration Register */
#define SPCR_PCIHPE   0x10000000	/* PCI Highest Priority Enable. */
#define SPCR_PCIHPE_SHIFT	(31-3)
#define SPCR_PCIPR    0x03000000	/* PCI bridge system bus request priority. */
#define SPCR_PCIPR_SHIFT	(31-7)
#define SPCR_OPT      0x00800000	/* Optimize */
#define SPCR_TBEN     0x00400000	/* E300 PowerPC core time base unit enable. */
#define SPCR_TBEN_SHIFT		(31-9)
#define SPCR_COREPR   0x00300000	/* E300 PowerPC Core system bus request priority. */
#define SPCR_COREPR_SHIFT	(31-11)
#if defined (CONFIG_MPC8349)
#define SPCR_TSEC1DP  0x00003000	/* TSEC1 data priority. */
#define SPCR_TSEC1DP_SHIFT	(31-19)
#define SPCR_TSEC1BDP 0x00000C00	/* TSEC1 buffer descriptor priority. */
#define SPCR_TSEC1BDP_SHIFT	(31-21)
#define SPCR_TSEC1EP  0x00000300	/* TSEC1 emergency priority. */
#define SPCR_TSEC1EP_SHIFT	(31-23)
#define SPCR_TSEC2DP  0x00000030	/* TSEC2 data priority. */
#define SPCR_TSEC2DP_SHIFT	(31-27)
#define SPCR_TSEC2BDP 0x0000000C	/* TSEC2 buffer descriptor priority. */
#define SPCR_TSEC2BDP_SHIFT	(31-29)
#define SPCR_TSEC2EP  0x00000003	/* TSEC2 emergency priority. */
#define SPCR_TSEC2EP_SHIFT	(31-31)
#define SPCR_RES      ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \
			| SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \
			| SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP)
#elif defined (CONFIG_MPC8360)
#define SPCR_RES      ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_OPT|SPCR_TBEN|SPCR_COREPR)
#endif
	u32 sicrl;		/* System General Purpose Register Low */
#if defined (CONFIG_MPC8349)
#define SICRL_LDP_A   0x80000000
#define SICRL_USB1    0x40000000
#define SICRL_USB0    0x20000000
#define SICRL_UART    0x0C000000
#define SICRL_GPIO1_A 0x02000000
#define SICRL_GPIO1_B 0x01000000
#define SICRL_GPIO1_C 0x00800000
#define SICRL_GPIO1_D 0x00400000
#define SICRL_GPIO1_E 0x00200000
#define SICRL_GPIO1_F 0x00180000
#define SICRL_GPIO1_G 0x00040000
#define SICRL_GPIO1_H 0x00020000
#define SICRL_GPIO1_I 0x00010000
#define SICRL_GPIO1_J 0x00008000
#define SICRL_GPIO1_K 0x00004000
#define SICRL_GPIO1_L 0x00003000
#define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \
			| SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \
			| SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \
			| SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \
			| SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L )
#elif defined (CONFIG_MPC8360)
#define SICRL_LDP_A   0xC0000000
#define SICRL_LCLK_1  0x10000000
#define SICRL_LCLK_2  0x08000000
#define SICRL_SRCID_A 0x03000000
#define SICRL_IRQ_CKSTP_A 0x00C00000
#define SICRL_RES     ~(SICRL_LDP_A | SICRL_LCLK_1 | SICRL_LCLK_2 | \
			SICRL_SRCID_A | SICRL_IRQ_CKSTP_A)
#endif
	u32 sicrh;		/* System General Purpose Register High */
#define SICRH_DDR     0x80000000
#if defined (CONFIG_MPC8349)
#define SICRH_TSEC1_A 0x10000000
#define SICRH_TSEC1_B 0x08000000
#define SICRH_TSEC1_C 0x04000000
#define SICRH_TSEC1_D 0x02000000
#define SICRH_TSEC1_E 0x01000000
#define SICRH_TSEC1_F 0x00800000
#define SICRH_TSEC2_A 0x00400000
#define SICRH_TSEC2_B 0x00200000
#define SICRH_TSEC2_C 0x00100000
#define SICRH_TSEC2_D 0x00080000
#define SICRH_TSEC2_E 0x00040000
#define SICRH_TSEC2_F 0x00020000
#define SICRH_TSEC2_G 0x00010000
#define SICRH_TSEC2_H 0x00008000
#define SICRH_GPIO2_A 0x00004000
#define SICRH_GPIO2_B 0x00002000
#define SICRH_GPIO2_C 0x00001000
#define SICRH_GPIO2_D 0x00000800
#define SICRH_GPIO2_E 0x00000400
#define SICRH_GPIO2_F 0x00000200
#define SICRH_GPIO2_G 0x00000180
#define SICRH_GPIO2_H 0x00000060
#define SICRH_TSOBI1  0x00000002
#define SICRH_TSOBI2  0x00000001
#define SICRH_RES     ~(  SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \
			| SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \
			| SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \
			| SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \
			| SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \
			| SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \
			| SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \
			| SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \
			| SICRH_TSOBI2)
#elif defined (CONFIG_MPC8360)
#define SICRH_SECONDARY_DDR 0x40000000
#define SICRH_SDDROE   0x02000000	/* SDDRIOE bit from reset configuration word high. */
#define SICRH_UC1EOBI  0x00000004	/* UCC1 Ethernet Output Buffer Impedance. */
#define SICRH_UC2E1OBI 0x00000002	/* UCC2 Ethernet pin option 1 Output Buffer Impedance. */
#define SICRH_UC2E2OBI 0x00000001	/* UCC2 Ethernet pin option 2 Output Buffer Impedance. */
#define SICRH_RES     ~(SICRH_DDR | SICRH_SECONDARY_DDR | SICRH_SDDROE | \
			SICRH_UC2E1OBI | SICRH_UC2E2OBI | SICRH_UC2E2OBI)
#endif
	u8 res6[0xE4];
} sysconf83xx_t;

/*
 * Watch Dog Timer (WDT) Registers
 */
typedef struct wdt83xx {
	u8 res0[4];
	u32 swcrr;		/* System watchdog control register */
	u32 swcnr;		/* System watchdog count register */
#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
#define SWCNR_RES  ~(SWCNR_SWCN)
	u8 res1[2];
	u16 swsrr;		/* System watchdog service register */
#define SWSRR_WS 0x0000FFFF	/* Software Watchdog Service Field. */
	u8 res2[0xF0];
} wdt83xx_t;

/*
 * RTC/PIT Module Registers
 */
typedef struct rtclk83xx {
	u32 cnr;		/* control register */
#define CNR_CLEN 0x00000080	/* Clock Enable Control Bit  */
#define CNR_CLIN 0x00000040	/* Input Clock Control Bit  */
#define CNR_AIM	 0x00000002	/* Alarm Interrupt Mask Bit  */
#define CNR_SIM	 0x00000001	/* Second Interrupt Mask Bit  */
#define CNR_RES	 ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM)
	u32 ldr;		/* load register */
#define LDR_CLDV 0xFFFFFFFF	/* Contains the 32-bit value to be
				 * loaded in a 32-bit RTC counter.*/
	u32 psr;		/* prescale register */
#define PSR_PRSC 0xFFFFFFFF	/*  RTC Prescaler bits. */
	u32 ctr;		/* Counter value field register */
#define CRT_CNTV 0xFFFFFFFF	/* RTC Counter value field. */
	u32 evr;		/* event register */
#define RTEVR_SIF  0x00000001	/* Second Interrupt Flag Bit  */
#define RTEVR_AIF  0x00000002	/* Alarm Interrupt Flag Bit  */
#define RTEVR_RES ~(RTEVR_SIF | RTEVR_AIF)
#define PTEVR_PIF  0x00000001	/* Periodic interrupt flag bit. */
#define PTEVR_RES ~(PTEVR_PIF)
	u32 alr;		/* alarm register */
	u8 res0[0xE8];
} rtclk83xx_t;

/*
 * Global timper module
 */

typedef struct gtm83xx {
	u8 cfr1;		/* Timer1/2 Configuration  */
#define CFR1_PCAS 0x80		/* Pair Cascade mode  */
#define CFR1_BCM  0x40		/* Backward compatible mode  */
#define CFR1_STP2 0x20		/* Stop timer  */
#define CFR1_RST2 0x10		/* Reset timer	*/
#define CFR1_GM2  0x08		/* Gate mode for pin 2	*/
#define CFR1_GM1  0x04		/* Gate mode for pin 1	*/
#define CFR1_STP1 0x02		/* Stop timer  */
#define CFR1_RST1 0x01		/* Reset timer	*/
#define CFR1_RES ~(CFR1_PCAS | CFR1_STP2 | CFR1_RST2 | CFR1_GM2 |\
		 CFR1_GM1 | CFR1_STP1 | CFR1_RST1)
	u8 res0[3];
	u8 cfr2;		/* Timer3/4 Configuration  */
#define CFR2_PCAS 0x80		/* Pair Cascade mode  */
#define CFR2_SCAS 0x40		/* Super Cascade mode  */
#define CFR2_STP4 0x20		/* Stop timer  */
#define CFR2_RST4 0x10		/* Reset timer	*/
#define CFR2_GM4  0x08		/* Gate mode for pin 4	*/
#define CFR2_GM3  0x04		/* Gate mode for pin 3	*/
#define CFR2_STP3 0x02		/* Stop timer  */
#define CFR2_RST3 0x01		/* Reset timer	*/
	u8 res1[10];
	u16 mdr1;		/* Timer1 Mode Register	 */
#define MDR_SPS	 0xff00		/* Secondary Prescaler value  */
#define MDR_CE	 0x00c0		/* Capture edge and enable interrupt  */
#define MDR_OM	 0x0020		/* Output mode	*/
#define MDR_ORI	 0x0010		/* Output reference interrupt enable  */
#define MDR_FRR	 0x0008		/* Free run/restart  */
#define MDR_ICLK 0x0006		/* Input clock source for the timer  */
#define MDR_GE	 0x0001		/* Gate enable	*/
	u16 mdr2;		/* Timer2 Mode Register	 */
	u16 rfr1;		/* Timer1 Reference Register  */
	u16 rfr2;		/* Timer2 Reference Register  */
	u16 cpr1;		/* Timer1 Capture Register  */
	u16 cpr2;		/* Timer2 Capture Register  */
	u16 cnr1;		/* Timer1 Counter Register  */
	u16 cnr2;		/* Timer2 Counter Register  */
	u16 mdr3;		/* Timer3 Mode Register	 */
	u16 mdr4;		/* Timer4 Mode Register	 */
	u16 rfr3;		/* Timer3 Reference Register  */
	u16 rfr4;		/* Timer4 Reference Register  */
	u16 cpr3;		/* Timer3 Capture Register  */
	u16 cpr4;		/* Timer4 Capture Register  */
	u16 cnr3;		/* Timer3 Counter Register  */
	u16 cnr4;		/* Timer4 Counter Register  */
	u16 evr1;		/* Timer1 Event Register  */
	u16 evr2;		/* Timer2 Event Register  */
	u16 evr3;		/* Timer3 Event Register  */
	u16 evr4;		/* Timer4 Event Register  */
#define GTEVR_REF 0x0002	/* Output reference event  */
#define GTEVR_CAP 0x0001	/* Counter Capture event   */
#define GTEVR_RES ~(EVR_CAP|EVR_REF)
	u16 psr1;		/* Timer1 Prescaler Register  */
	u16 psr2;		/* Timer2 Prescaler Register  */
	u16 psr3;		/* Timer3 Prescaler Register  */
	u16 psr4;		/* Timer4 Prescaler Register  */
#define GTPSR_PPS  0x00FF	/* Primary Prescaler Bits. */
#define GTPSR_RES  ~(GTPSR_PPS)
	u8 res[0xC0];
} gtm83xx_t;

/*
 * Integrated Programmable Interrupt Controller
 */
typedef struct ipic83xx {
	u32 sicfr;		/*  System Global Interrupt Configuration Register (SICFR)  */
#define SICFR_HPI  0x7f000000	/*  Highest Priority Interrupt	*/
#define SICFR_MPSB 0x00400000	/*  Mixed interrupts Priority Scheme for group B  */
#define SICFR_MPSA 0x00200000	/*  Mixed interrupts Priority Scheme for group A  */
#define SICFR_IPSD 0x00080000	/*  Internal interrupts Priority Scheme for group D  */
#define SICFR_IPSA 0x00010000	/*  Internal interrupts Priority Scheme for group A  */
#define SICFR_HPIT 0x00000300	/*  HPI priority position IPIC output interrupt Type  */
#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT)
	u32 sivcr;		/*  System Global Interrupt Vector Register (SIVCR)  */
#define SICVR_IVECX 0xfc000000	/*  Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation)  */
#define SICVR_IVEC  0x0000007f	/*  Interrupt vector  */
#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC)
	u32 sipnr_h;		/*  System Internal Interrupt Pending Register - High (SIPNR_H)	 */
#if defined (CONFIG_MPC8349)
#define SIIH_TSEC1TX 0x80000000 /*  TSEC1 Tx interrupt	*/
#define SIIH_TSEC1RX 0x40000000 /*  TSEC1 Rx interrupt	*/
#define SIIH_TSEC1ER 0x20000000 /*  TSEC1 Eror interrupt  */
#define SIIH_TSEC2TX 0x10000000 /*  TSEC2 Tx interrupt	*/
#define SIIH_TSEC2RX 0x08000000 /*  TSEC2 Rx interrupt	*/
#define SIIH_TSEC2ER 0x04000000 /*  TSEC2 Eror interrupt  */
#define SIIH_USB2DR  0x02000000 /*  USB2 DR interrupt  */
#define SIIH_USB2MPH 0x01000000 /*  USB2 MPH interrupt	*/
#endif
#if defined (CONFIG_MPC8360)
#define SIIH_H_QE_H   0x80000000	/*  QE high interrupt */
#define SIIH_H_QE_L   0x40000000	/*  QE low interrupt */
#endif
#define SIIH_UART1   0x00000080 /*  UART1 interrupt  */
#define SIIH_UART2   0x00000040 /*  UART2 interrupt  */
#define SIIH_SEC     0x00000020 /*  SEC interrupt  */
#define SIIH_I2C1    0x00000004 /*  I2C1 interrupt  */
#define SIIH_I2C2    0x00000002 /*  I2C2 interrupt  */
#if defined (CONFIG_MPC8349)
#define SIIH_SPI     0x00000001 /*  SPI interrupt  */
#define SIIH_RES	~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
			| SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
			| SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \
			| SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \
			| SIIH_I2C2 | SIIH_SPI)
#endif
#if defined (CONFIG_MPC8360)
#define SIIH_RES       ~(SIIH_H_QE_H | SIIH_H_QE_L | SIIH_H_UART1 | \
			SIIH_H_UART2| SIIH_H_SEC  | SIIH_H_I2C1 |SIIH_H_I2C2)