📄 p3mx.h
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CONFIG_EXTRA_ENV_SETTINGS_COMMON \ "hostname=p3m750\0" \ "bootfile=/tftpboot/p3mx/vxWorks.st\0" \ "kernel_addr=fc000000\0" \ "ramdisk_addr=fc180000\0" \ "vxfile=p3m750/vxWorks\0" \ "vxuser=ddg\0" \ "vxpass=ddg\0" \ "vxtarget=target\0" \ "vxflags=0x8\0" \ "vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} " \ "e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} " \ "f=${vxflags}\0"#elif defined (CONFIG_P3M7448)#define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_EXTRA_ENV_SETTINGS_COMMON \ "hostname=p3m7448\0"#endif#if defined (CONFIG_P3M750)#define CONFIG_BOOTCOMMAND "tftp;run vxargs;bootvx"#elif defined (CONFIG_P3M7448)#define CONFIG_BOOTCOMMAND " "#endif#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ CONFIG_BOOTP_BOOTFILESIZE)#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ CFG_CMD_DATE | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ CFG_CMD_NET | \ CFG_CMD_NFS | \ CFG_CMD_PING | \ CFG_CMD_REGINFO | \ CFG_CMD_PCI | \ CFG_CMD_CACHE | \ CFG_CMD_SDRAM)/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */#include <cmd_confdefs.h>/*----------------------------------------------------------------------- * Miscellaneous configurable options *----------------------------------------------------------------------*/#define CFG_HUSH_PARSER#define CFG_PROMPT_HUSH_PS2 "> "#define CFG_LONGHELP /* undef to save memory */#define CFG_PROMPT "=> " /* Monitor Command Prompt */#if (CONFIG_COMMANDS & CFG_CMD_KGDB)#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */#else#define CFG_CBSIZE 256 /* Console I/O Buffer Size */#endif#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */#define CFG_MAXARGS 16 /* max number of command args */#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */#define CFG_MEMTEST_START 0x0400000 /* memtest works on */#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */#define CFG_LOAD_ADDR 0x08000000 /* default load address */#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */#define CONFIG_CMDLINE_EDITING 1 /* add command line history */#define CONFIG_LOOPW 1 /* enable loopw command */#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */#define CONFIG_VERSION_VARIABLE 1 /* include version env variable *//*----------------------------------------------------------------------- * Marvell MV64460 config settings *----------------------------------------------------------------------*//* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */#if defined (CONFIG_P3M750)#define CFG_BOOT_PAR 0x8FDFF87F /* 16 bit flash, disable burst*/#elif defined (CONFIG_P3M7448)#define CFG_BOOT_PAR 0x8FEFFFFF /* 32 bit flash, burst enabled */#endif/* * MPP[0] Serial Port 0 TxD TxD OUT Connected to P14 (buffered) * MPP[1] Serial Port 0 RxD RxD IN Connected to P14 (buffered) * MPP[2] NC * MPP[3] Serial Port 1 TxD TxD OUT Connected to P14 (buffered) * MPP[4] PCI Monarch# GPIO IN Connected to P12 * MPP[5] Serial Port 1 RxD RxD IN Connected to P14 (buffered) * MPP[6] PMC Carrier Interrupt 0 Int IN Connected to P14 * MPP[7] PMC Carrier Interrupt 1 Int IN Connected to P14 * MPP[8] Reserved Do not use * MPP[9] Reserved Do not use * MPP[10] Reserved Do not use * MPP[11] Reserved Do not use * MPP[12] Phy 0 Interrupt Int IN * MPP[13] Phy 1 Interrupt Int IN * MPP[14] NC * MPP[15] NC * MPP[16] PCI Interrupt C Int IN Connected to P11 * MPP[17] PCI Interrupt D Int IN Connected to P11 * MPP[18] Watchdog NMI# GPIO IN Connected to MPP[24] * MPP[19] Watchdog Expired# WDE OUT Connected to rst logic * MPP[20] Watchdog Status WD_STS IN Read back of rst by watchdog * MPP[21] NC * MPP[22] GP LED Green GPIO OUT * MPP[23] GP LED Red GPIO OUT * MPP[24] Watchdog NMI# Int OUT * MPP[25] NC * MPP[26] NC * MPP[27] PCI Interrupt A Int IN Connected to P11 * MPP[28] NC * MPP[29] PCI Interrupt B Int IN Connected to P11 * MPP[30] Module reset GPIO OUT Board reset * MPP[31] PCI EReady GPIO IN Connected to P12 */#define CFG_MPP_CONTROL_0 0x00303022#define CFG_MPP_CONTROL_1 0x00000000#define CFG_MPP_CONTROL_2 0x00004000#define CFG_MPP_CONTROL_3 0x00000004#define CFG_GPP_LEVEL_CONTROL 0x280730D0/*---------------------------------------------------------------------- * Initial BAT mappings *//* NOTES: * 1) GUARDED and WRITE_THRU not allowed in IBATS * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT *//* SDRAM */#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)#define CFG_DBAT0U CFG_IBAT0U/* init ram */#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)#define CFG_DBAT1L CFG_IBAT1L#define CFG_DBAT1U CFG_IBAT1U/* PCI0, PCI1 in one BAT */#define CFG_IBAT2L BATL_NO_ACCESS#define CFG_IBAT2U CFG_DBAT2U#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)/* GT regs, bootrom, all the devices, PCI I/O */#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)#define CFG_DBAT3U CFG_IBAT3U#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)#define CFG_DBAT4U CFG_IBAT4U/* set rest out of range for Linux !!!!!!!!!!! *//* IBAT5 and DBAT5 */#define CFG_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)#define CFG_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)#define CFG_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)#define CFG_DBAT5U CFG_IBAT5U/* IBAT6 and DBAT6 */#define CFG_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)#define CFG_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)#define CFG_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)#define CFG_DBAT6U CFG_IBAT6U/* IBAT7 and DBAT7 */#define CFG_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)#define CFG_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)#define CFG_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)#define CFG_DBAT7U CFG_IBAT7U/* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */#define CFG_VXWORKS_MAC_PTR 0x42010000 /* use some memory in SRAM that's not used!!! *//*----------------------------------------------------------------------- * Cache Configuration */#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */#if (CONFIG_COMMANDS & CFG_CMD_KGDB)#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */#endif/*----------------------------------------------------------------------- * L2CR setup -- make sure this is right for your board! * look in include/mpc74xx.h for the defines used here */#define CFG_L2#if defined (CONFIG_750CX) || defined (CONFIG_750FX)#define L2_INIT 0#else#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)#endif#define L2_ENABLE (L2_INIT | L2CR_L2E)/* * Internal Definitions * * Boot Flags */#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */#define BOOTFLAG_WARM 0x02 /* Software reboot */#endif /* __CONFIG_H */⌨️ 快捷键说明
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