uec.h

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/* Rx interrupt coalescing entry, each Rx queue has one this entry.
*/
typedef struct uec_rx_interrupt_coalescing_entry {
	u32   maxvalue;
	u32   counter;
} __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t;

typedef struct uec_rx_interrupt_coalescing_table {
	uec_rx_interrupt_coalescing_entry_t   entry[MAX_RX_QUEUES];
} __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t;

/* RxBD queue entry, each Rx queue has one this entry.
*/
typedef struct uec_rx_bd_queues_entry {
	u32   bdbaseptr;         /* BD base pointer          */
	u32   bdptr;             /* BD pointer               */
	u32   externalbdbaseptr; /* external BD base pointer */
	u32   externalbdptr;     /* external BD pointer      */
} __attribute__ ((packed)) uec_rx_bd_queues_entry_t;

/* Rx global paramter table
*/
typedef struct uec_rx_global_pram {
	u32  remoder;             /* ethernet mode reg. */
	u32  rqptr;               /* base pointer to the Rx Queues */
	u32  res0[0x1];
	u8   res1[0x20-0xC];
	u16  typeorlen;
	u8   res2[0x1];
	u8   rxgstpack;           /* ack on GRACEFUL STOP RX command */
	u32  rxrmonbaseptr;       /* Rx RMON statistics base */
	u8   res3[0x30-0x28];
	u32  intcoalescingptr;    /* Interrupt coalescing table pointer */
	u8   res4[0x36-0x34];
	u8   rstate;
	u8   res5[0x46-0x37];
	u16  mrblr;               /* max receive buffer length reg. */
	u32  rbdqptr;             /* RxBD parameter table description */
	u16  mflr;                /* max frame length reg. */
	u16  minflr;              /* min frame length reg. */
	u16  maxd1;               /* max dma1 length reg. */
	u16  maxd2;               /* max dma2 length reg. */
	u32  ecamptr;             /* external CAM address */
	u32  l2qt;                /* VLAN priority mapping table. */
	u32  l3qt[0x8];           /* IP   priority mapping table. */
	u16  vlantype;            /* vlan type */
	u16  vlantci;             /* default vlan tci */
	u8   addressfiltering[64];/* address filtering data structure */
	u32  exfGlobalParam;      /* extended filtering global parameters */
	u8   res6[0x100-0xC4];    /* Initialize to zero */
} __attribute__ ((packed)) uec_rx_global_pram_t;

#define GRACEFUL_STOP_ACKNOWLEDGE_RX            0x01


/****** UEC common ******/
/* UCC statistics - hardware counters
*/
typedef struct uec_hardware_statistics {
	u32 tx64;
	u32 tx127;
	u32 tx255;
	u32 rx64;
	u32 rx127;
	u32 rx255;
	u32 txok;
	u16 txcf;
	u32 tmca;
	u32 tbca;
	u32 rxfok;
	u32 rxbok;
	u32 rbyt;
	u32 rmca;
	u32 rbca;
} __attribute__ ((packed)) uec_hardware_statistics_t;

/* InitEnet command parameter
*/
typedef struct uec_init_cmd_pram {
	u8   resinit0;
	u8   resinit1;
	u8   resinit2;
	u8   resinit3;
	u16  resinit4;
	u8   res1[0x1];
	u8   largestexternallookupkeysize;
	u32  rgftgfrxglobal;
	u32  rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */
	u8   res2[0x38 - 0x30];
	u32  txglobal;				   /* tx global  */
	u32  txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
	u8   res3[0x1];
} __attribute__ ((packed)) uec_init_cmd_pram_t;

#define ENET_INIT_PARAM_RGF_SHIFT		(32 - 4)
#define ENET_INIT_PARAM_TGF_SHIFT		(32 - 8)

#define ENET_INIT_PARAM_RISC_MASK		0x0000003f
#define ENET_INIT_PARAM_PTR_MASK		0x00ffffc0
#define ENET_INIT_PARAM_SNUM_MASK		0xff000000
#define ENET_INIT_PARAM_SNUM_SHIFT		24

#define ENET_INIT_PARAM_MAGIC_RES_INIT0		0x06
#define ENET_INIT_PARAM_MAGIC_RES_INIT1		0x30
#define ENET_INIT_PARAM_MAGIC_RES_INIT2		0xff
#define ENET_INIT_PARAM_MAGIC_RES_INIT3		0x00
#define ENET_INIT_PARAM_MAGIC_RES_INIT4		0x0400

/* structure representing 82xx Address Filtering Enet Address in PRAM
*/
typedef struct uec_82xx_enet_address {
	u8   res1[0x2];
	u16  h;       /* address (MSB) */
	u16  m;       /* address       */
	u16  l;       /* address (LSB) */
} __attribute__ ((packed)) uec_82xx_enet_address_t;

/* structure representing 82xx Address Filtering PRAM
*/
typedef struct uec_82xx_address_filtering_pram {
	u32  iaddr_h;        /* individual address filter, high */
	u32  iaddr_l;        /* individual address filter, low  */
	u32  gaddr_h;        /* group address filter, high      */
	u32  gaddr_l;        /* group address filter, low       */
	uec_82xx_enet_address_t    taddr;
	uec_82xx_enet_address_t    paddr[4];
	u8                         res0[0x40-0x38];
} __attribute__ ((packed)) uec_82xx_address_filtering_pram_t;

/* Buffer Descriptor
*/
typedef struct buffer_descriptor {
	u16 status;
	u16 len;
	u32 data;
} __attribute__ ((packed)) qe_bd_t, *p_bd_t;

#define	SIZEOFBD		sizeof(qe_bd_t)

/* Common BD flags
*/
#define BD_WRAP			0x2000
#define BD_INT			0x1000
#define BD_LAST			0x0800
#define BD_CLEAN		0x3000

/* TxBD status flags
*/
#define TxBD_READY		0x8000
#define TxBD_PADCRC		0x4000
#define TxBD_WRAP		BD_WRAP
#define TxBD_INT		BD_INT
#define TxBD_LAST		BD_LAST
#define TxBD_TXCRC		0x0400
#define TxBD_DEF		0x0200
#define TxBD_PP			0x0100
#define TxBD_LC			0x0080
#define TxBD_RL			0x0040
#define TxBD_RC			0x003C
#define TxBD_UNDERRUN		0x0002
#define TxBD_TRUNC		0x0001

#define TxBD_ERROR		(TxBD_UNDERRUN | TxBD_TRUNC)

/* RxBD status flags
*/
#define RxBD_EMPTY		0x8000
#define RxBD_OWNER		0x4000
#define RxBD_WRAP		BD_WRAP
#define RxBD_INT		BD_INT
#define RxBD_LAST		BD_LAST
#define RxBD_FIRST		0x0400
#define RxBD_CMR		0x0200
#define RxBD_MISS		0x0100
#define RxBD_BCAST		0x0080
#define RxBD_MCAST		0x0040
#define RxBD_LG			0x0020
#define RxBD_NO			0x0010
#define RxBD_SHORT		0x0008
#define RxBD_CRCERR		0x0004
#define RxBD_OVERRUN		0x0002
#define RxBD_IPCH		0x0001

#define RxBD_ERROR		(RxBD_LG | RxBD_NO | RxBD_SHORT | \
				 RxBD_CRCERR | RxBD_OVERRUN)

/* BD access macros
*/
#define BD_STATUS(_bd)			(((p_bd_t)(_bd))->status)
#define BD_STATUS_SET(_bd, _val)	(((p_bd_t)(_bd))->status = _val)
#define BD_LENGTH(_bd)			(((p_bd_t)(_bd))->len)
#define BD_LENGTH_SET(_bd, _val)	(((p_bd_t)(_bd))->len = _val)
#define BD_DATA_CLEAR(_bd)		(((p_bd_t)(_bd))->data = 0)
#define BD_IS_DATA(_bd)			(((p_bd_t)(_bd))->data)
#define BD_DATA(_bd)			((u8 *)(((p_bd_t)(_bd))->data))
#define BD_DATA_SET(_bd, _data)		(((p_bd_t)(_bd))->data = (u32)(_data))
#define BD_ADVANCE(_bd,_status,_base)	\
	(((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd))

/* Rx Prefetched BDs
*/
typedef struct uec_rx_prefetched_bds {
    qe_bd_t   bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
} __attribute__ ((packed)) uec_rx_prefetched_bds_t;

/* Alignments
 */
#define UEC_RX_GLOBAL_PRAM_ALIGNMENT				64
#define UEC_TX_GLOBAL_PRAM_ALIGNMENT				64
#define UEC_THREAD_RX_PRAM_ALIGNMENT				128
#define UEC_THREAD_TX_PRAM_ALIGNMENT				64
#define UEC_THREAD_DATA_ALIGNMENT				256
#define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT		32
#define UEC_SCHEDULER_ALIGNMENT					4
#define UEC_TX_STATISTICS_ALIGNMENT				4
#define UEC_RX_STATISTICS_ALIGNMENT				4
#define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT			4
#define UEC_RX_BD_QUEUES_ALIGNMENT				8
#define UEC_RX_PREFETCHED_BDS_ALIGNMENT				128
#define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT	4
#define UEC_RX_BD_RING_ALIGNMENT				32
#define UEC_TX_BD_RING_ALIGNMENT				32
#define UEC_MRBLR_ALIGNMENT					128
#define UEC_RX_BD_RING_SIZE_ALIGNMENT				4
#define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT			32
#define UEC_RX_DATA_BUF_ALIGNMENT				64

#define UEC_VLAN_PRIORITY_MAX					8
#define UEC_IP_PRIORITY_MAX					64
#define UEC_TX_VTAG_TABLE_ENTRY_MAX				8
#define UEC_RX_BD_RING_SIZE_MIN					8
#define UEC_TX_BD_RING_SIZE_MIN					2

/* Ethernet speed
*/
typedef enum enet_speed {
	ENET_SPEED_10BT,   /* 10 Base T */
	ENET_SPEED_100BT,  /* 100 Base T */
	ENET_SPEED_1000BT  /* 1000 Base T */
} enet_speed_e;

/* Ethernet Address Type.
*/
typedef enum enet_addr_type {
	ENET_ADDR_TYPE_INDIVIDUAL,
	ENET_ADDR_TYPE_GROUP,
	ENET_ADDR_TYPE_BROADCAST
} enet_addr_type_e;

/* TBI / MII Set Register
*/
typedef enum enet_tbi_mii_reg {
	ENET_TBI_MII_CR        = 0x00,
	ENET_TBI_MII_SR        = 0x01,
	ENET_TBI_MII_ANA       = 0x04,
	ENET_TBI_MII_ANLPBPA   = 0x05,
	ENET_TBI_MII_ANEX      = 0x06,
	ENET_TBI_MII_ANNPT     = 0x07,
	ENET_TBI_MII_ANLPANP   = 0x08,
	ENET_TBI_MII_EXST      = 0x0F,
	ENET_TBI_MII_JD        = 0x10,
	ENET_TBI_MII_TBICON    = 0x11
} enet_tbi_mii_reg_e;

/* UEC number of threads
*/
typedef enum uec_num_of_threads {
	UEC_NUM_OF_THREADS_1  = 0x1,  /* 1 */
	UEC_NUM_OF_THREADS_2  = 0x2,  /* 2 */
	UEC_NUM_OF_THREADS_4  = 0x0,  /* 4 */
	UEC_NUM_OF_THREADS_6  = 0x3,  /* 6 */
	UEC_NUM_OF_THREADS_8  = 0x4   /* 8 */
} uec_num_of_threads_e;

/* UEC ethernet interface type
*/
typedef enum enet_interface {
	ENET_10_MII,
	ENET_10_RMII,
	ENET_10_RGMII,
	ENET_100_MII,
	ENET_100_RMII,
	ENET_100_RGMII,
	ENET_1000_GMII,
	ENET_1000_RGMII,
	ENET_1000_TBI,
	ENET_1000_RTBI
} enet_interface_e;

/* UEC initialization info struct
*/
typedef struct uec_info {
	ucc_fast_info_t			uf_info;
	uec_num_of_threads_e		num_threads_tx;
	uec_num_of_threads_e		num_threads_rx;
	qe_risc_allocation_e		riscTx;
	qe_risc_allocation_e		riscRx;
	u16				rx_bd_ring_len;
	u16				tx_bd_ring_len;
	u8				phy_address;
	enet_interface_e		enet_interface;
} uec_info_t;

/* UEC driver initialized info
*/
#define MAX_RXBUF_LEN			1536
#define MAX_FRAME_LEN			1518
#define MIN_FRAME_LEN			64
#define MAX_DMA1_LEN			1520
#define MAX_DMA2_LEN			1520

/* UEC driver private struct
*/
typedef struct uec_private {
	uec_info_t			*uec_info;
	ucc_fast_private_t		*uccf;
	struct eth_device		*dev;
	uec_t				*uec_regs;
	/* enet init command parameter */
	uec_init_cmd_pram_t		*p_init_enet_param;
	u32				init_enet_param_offset;
	/* Rx and Tx paramter */
	uec_rx_global_pram_t		*p_rx_glbl_pram;
	u32				rx_glbl_pram_offset;
	uec_tx_global_pram_t		*p_tx_glbl_pram;
	u32				tx_glbl_pram_offset;
	uec_send_queue_mem_region_t	*p_send_q_mem_reg;
	u32				send_q_mem_reg_offset;
	uec_thread_data_tx_t		*p_thread_data_tx;
	u32				thread_dat_tx_offset;
	uec_thread_data_rx_t		*p_thread_data_rx;
	u32				thread_dat_rx_offset;
	uec_rx_bd_queues_entry_t	*p_rx_bd_qs_tbl;
	u32				rx_bd_qs_tbl_offset;
	/* BDs specific */
	u8				*p_tx_bd_ring;
	u32				tx_bd_ring_offset;
	u8				*p_rx_bd_ring;
	u32				rx_bd_ring_offset;
	u8				*p_rx_buf;
	u32				rx_buf_offset;
	volatile qe_bd_t		*txBd;
	volatile qe_bd_t		*rxBd;
	/* Status */
	int				mac_tx_enabled;
	int				mac_rx_enabled;
	int				grace_stopped_tx;
	int				grace_stopped_rx;
	int				the_first_run;
	/* PHY specific */
	struct uec_mii_info 		*mii_info;
	int				oldspeed;
	int				oldduplex;
	int				oldlink;
} uec_private_t;

#endif /* __UEC_H__ */