regsnd1.h

实现 32M的MP3+U盘的循环播放功能的原程序

/*-------------------------------------------------------------------------
REGSND1.H

Header file for AtmelWM T8xC51SND1
  
Copyright (c) 1988-2001 Keil Elektronik GmbH and Keil Software, Inc.
All rights reserved.
-------------------------------------------------------------------------*/

#ifndef _REGSND1_H_
#define _REGSND1_H_

/*_____ I N C L U D E S ____________________________________________________*/


/*_____ M A C R O S ________________________________________________________*/


/* C51 CORE */

sfr ACC = 0xE0;
sfr B   = 0xF0;
sfr PSW = 0xD0;
sfr SP  = 0x81;
sfr DPL = 0x82;
sfr DPH = 0x83;

sbit CY  = PSW ^ 7;
sbit AC  = PSW ^ 6;
sbit F0  = PSW ^ 5;
sbit RS1 = PSW ^ 4;
sbit RS0 = PSW ^ 3;
sbit OV  = PSW ^ 2;
sbit F1  = PSW ^ 1;
sbit P   = PSW ^ 0;


/* SYSTEM MANAGEMENT */

sfr PCON = 0x87;
sfr AUXR = 0x8E;
sfr AUXR1 = 0xA2;
sfr NVERS = 0xFB;


/* PLL & CLOCK */

sfr CKCON   = 0x8F;
sfr PLLCON  = 0xE9;
/////////////////////////////////////////
/////////////////////////////////////////
/////////////////////////////////////////by custom
#define R1 		(0x80)
#define R0		(0x40)
#define PLLRES	(0x08)
#define PLLEN	(0x02)
#define	PLOCK	(0x01)

sfr PLLDIV0 = 0xEE;
sfr PLLNDIV = 0xEE;
sfr PLLDIV1 = 0xEF;
sfr PLLRDIV = 0xEF;


/* INTERRUPT */

sfr IEN0    = 0xA8;
sfr IPL0    = 0xB8;
sfr IPH0    = 0xB7;
sfr IEN1    = 0xB1;
sfr IPL1    = 0xB2;
sfr IPH1    = 0xB3;


sbit EA     = IEN0 ^ 7;
sbit EAUD   = IEN0 ^ 6;
sbit EMP3   = IEN0 ^ 5;
sbit ES     = IEN0 ^ 4;
sbit ET1    = IEN0 ^ 3;
sbit EX1    = IEN0 ^ 2;
sbit ET0    = IEN0 ^ 1;
sbit EX0    = IEN0 ^ 0;

sbit IPLAUD = IPL0 ^ 6;
sbit IPLMP3 = IPL0 ^ 5;
sbit IPLS   = IPL0 ^ 4;
sbit IPLT1  = IPL0 ^ 3;
sbit IPLX1  = IPL0 ^ 2;
sbit IPLT0  = IPL0 ^ 1;
sbit IPLX0  = IPL0 ^ 0;


/* PORTS */

sfr P0      = 0x80;
sfr P1      = 0x90;
sfr P2      = 0xA0;
sfr P3      = 0xB0;
sfr P4      = 0xC0;
sfr P5      = 0xD8;

sbit P0_7   = P0 ^ 7;
sbit P0_6   = P0 ^ 6;
sbit P0_5   = P0 ^ 5;
sbit P0_4   = P0 ^ 4;
sbit P0_3   = P0 ^ 3;
sbit P0_2   = P0 ^ 2;
sbit P0_1   = P0 ^ 1;
sbit P0_0   = P0 ^ 0;

sbit P1_7   = P1 ^ 7;
sbit P1_6   = P1 ^ 6;
sbit P1_5   = P1 ^ 5;
sbit P1_4   = P1 ^ 4;
sbit P1_3   = P1 ^ 3;
sbit P1_2   = P1 ^ 2;
sbit P1_1   = P1 ^ 1;
sbit P1_0   = P1 ^ 0;
   
sbit SDA    = P1 ^ 7;
sbit SCL    = P1 ^ 6;
sbit KIN3   = P1 ^ 3;
sbit KIN2   = P1 ^ 2;
sbit KIN1   = P1 ^ 1;
sbit KIN0   = P1 ^ 0;
 
sbit P2_7   = P2 ^ 7;
sbit P2_6   = P2 ^ 6;
sbit P2_5   = P2 ^ 5;
sbit P2_4   = P2 ^ 4;
sbit P2_3   = P2 ^ 3;
sbit P2_2   = P2 ^ 2;
sbit P2_1   = P2 ^ 1;
sbit P2_0   = P2 ^ 0;

sbit P3_7   = P3 ^ 7;
sbit P3_6   = P3 ^ 6;
sbit P3_5   = P3 ^ 5;
sbit P3_4   = P3 ^ 4;
sbit P3_3   = P3 ^ 3;
sbit P3_2   = P3 ^ 2;
sbit P3_1   = P3 ^ 1;
sbit P3_0   = P3 ^ 0;

sbit RD     = P3 ^ 7;
sbit WR     = P3 ^ 6;
sbit T1     = P3 ^ 5;
sbit T0     = P3 ^ 4;
sbit INT1   = P3 ^ 3;
sbit INT0   = P3 ^ 2;
sbit TXD    = P3 ^ 1;
sbit RXD    = P3 ^ 0;

sbit P4_7   = P4 ^ 7;
sbit P4_6   = P4 ^ 6;
sbit P4_5   = P4 ^ 5;
sbit P4_4   = P4 ^ 4;
sbit P4_3   = P4 ^ 3;
sbit P4_2   = P4 ^ 2;
sbit P4_1   = P4 ^ 1;
sbit P4_0   = P4 ^ 0;

sbit SS_    = P4 ^ 3;
sbit SCK    = P4 ^ 2;
sbit MOSI   = P4 ^ 1;
sbit MISO   = P4 ^ 0;

sbit P5_3   = P5 ^ 3;
sbit P5_2   = P5 ^ 2;
sbit P5_1   = P5 ^ 1;
sbit P5_0   = P5 ^ 0;
 

/* FLASH MEMORY */

sfr FCON    = 0xD1;


/* TIMERS */

sfr TCON    = 0x88;
sfr TMOD    = 0x89;
sfr TL0     = 0x8A;
sfr TL1     = 0x8B;
sfr TH0     = 0x8C;
sfr TH1     = 0x8D;

sbit TF1    = TCON ^ 7;
sbit TR1    = TCON ^ 6;
sbit TF0    = TCON ^ 5;
sbit TR0    = TCON ^ 4;
sbit IE1    = TCON ^ 3;
sbit IT1    = TCON ^ 2;
sbit IE0    = TCON ^ 1;
sbit IT0    = TCON ^ 0;


/* WATCHDOG */

sfr WDTRST  = 0xA6;
sfr WDTPRG  = 0xA7;


/* MP3 DECODER */

sfr MP3CON  = 0xAA;
/////////////////////////////////////////
/////////////////////////////////////////
/////////////////////////////////////////by custom
#define MPEN			(0x80)
#define MPBBST		(0x40)
#define CRCEN		(0x20)
#define	MSKANC		(0x10)
#define	MSKREQ		(0x08)
#define	MSKLAY		(0x04)
#define	MSKSYN		(0x02)
#define	MSKCRC		(0x01)

sfr MP3STA  = 0xC8;
sfr MP3STA1 = 0xAF;
/////////////////////////////////////////
/////////////////////////////////////////
/////////////////////////////////////////by custom
#define	MPFREQ 		(0x10)
#define	MPBREQ 		(0x08)

sfr MP3DAT  = 0xAC;
sfr MP3ANC  = 0xAD;
sfr MP3VOL  = 0x9E;
sfr MP3VOR  = 0x9F;
sfr MP3BAS  = 0xB4;
sfr MP3MED  = 0xB5;
sfr MP3TRE  = 0xB6;
sfr MP3CLK  = 0xEB;

sbit MPANC  = MP3STA ^ 7;
sbit MPREQ  = MP3STA ^ 6;
sbit ERRLAY = MP3STA ^ 5;
sbit ERRSYN = MP3STA ^ 4;
sbit ERRCRC = MP3STA ^ 3;
sbit MPFS1  = MP3STA ^ 2;
sbit MPFS0  = MP3STA ^ 1;
sbit MPVER  = MP3STA ^ 0;

#define	MPANCC 	(0x80)
#define	MPREQC	    (0x40)
#define	ERRLAYC	(0x20)
#define	ERRSYNC	(0x10)
#define	ERRCRCC	(0x08)
#define	MPFS1C		(0x04)
#define	MPFS0C		(0x02)
#define	MPVERC		(0x01)

#define EUSB	(0x40)
#define EKB		(0x10)
#define EADC	(0x08)
#define ESPI	(0x04)
#define EI2C	(0x02)
#define EMMC	(0x01)

/* AUDIO INTERFACE */

sfr AUDCON0 = 0x9A;
sfr AUDCON1 = 0x9B;
sfr AUDSTA  = 0x9C;
sfr AUDDAT  = 0x9D;
sfr AUDCLK  = 0xEC;


/* USB CONTROLLER */

sfr USBCON  = 0xBC;
sfr USBADDR = 0xC6;
sfr USBINT  = 0xBD;
sfr USBIEN  = 0xBE;
sfr UEPNUM  = 0xC7;
sfr UEPCONX = 0xD4;
sfr UEPSTAX = 0xCE;
sfr UEPRST  = 0xD5;
sfr UEPINT  = 0xF8;
sfr UEPIEN  = 0xC2;
sfr UEPDATX = 0xCF;
sfr UBYCTX  = 0xE2;
sfr UBYCTLX = 0xE2;
sfr UFNUML  = 0xBA;
sfr UFNUMH  = 0xBB;
sfr USBCLK  = 0xEA;
sfr UDPADDH = 0xD7;
sfr UDPADDL = 0xD6;

sbit EP3INT = UEPINT ^ 3;
sbit EP2INT = UEPINT ^ 2;
sbit EP1INT = UEPINT ^ 1;
sbit EP0INT = UEPINT ^ 0;


/* MMC CONTROLLER */

sfr MMDAT   = 0xDC;
sfr MMCMD   = 0xDD;
sfr MMSTA   = 0xDE;
sfr MMMSK   = 0xDF;
sfr MMCON0  = 0xE4;
sfr MMCON1  = 0xE5;
sfr MMCON2  = 0xE6;
sfr MMINT   = 0xE7;
sfr MMCLK   = 0xED;


/* IDE CONTROLLER */

sfr DAT16H  = 0xF9;


/* UART */

sfr SCON    = 0x98;
sfr SBUF    = 0x99;
sfr SADDR   = 0xA9;
sfr SADEN   = 0xB9;

sbit SM0    = SCON ^ 7;
sbit FE     = SCON ^ 7;
sbit SM1    = SCON ^ 6;
sbit SM2    = SCON ^ 5;
sbit REN    = SCON ^ 4;
sbit TB8    = SCON ^ 3;
sbit RB8    = SCON ^ 2;
sbit TI     = SCON ^ 1;
sbit RI     = SCON ^ 0;


/* SPI CONTROLLER */

sfr SPCON   = 0xC3;
sfr SPSTA   = 0xC4;
sfr SPDAT   = 0xC5;


/* I2C CONTROLLER */

sfr SSCON   = 0x93;
sfr SSSTA   = 0x94;
sfr SSDAT   = 0x95;
sfr SSADR   = 0x96;


/* KEYBOARD */

sfr KBCON   = 0xA3;
sfr KBSTA   = 0xA4;


/* ADC CONVERTER */

sfr ADCON   = 0xF3;
sfr ADDL    = 0xF4;
sfr ADDH    = 0xF5;
sfr ADCLK   = 0xF2;


/*------------------------------------------------
Interrupt Vectors:
Interrupt Address = (Number * 8) + 3
------------------------------------------------*/
#define IE0_VECTOR	0  /* 0x03 External Interrupt 0 */
#define TF0_VECTOR	1  /* 0x0B Timer 0 */
#define IE1_VECTOR	2  /* 0x13 External Interrupt 1 */
#define TF1_VECTOR	3  /* 0x1B Timer 1 */
#define SIO_VECTOR	4  /* 0x23 Serial port */

/*------------------------------------------------
custom
------------------------------------------------*/
//#define MP3_VECTOR  5  /*0x2B MP3 decoder*/ 
#define KEY_VECTOR  11

/*------------------------------------------------
------------------------------------------------*/


#endif  /* _REGSND1_H_ */