📄 iodefine.h
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unsigned char SUM_U1RB:1; /* Error sum flag */
}BIT;
struct{
unsigned char U1RBL; /* Low 8 bit */
unsigned char U1RBH; /* High 8 bit */
}BYTE;
unsigned short WORD;
};
/*------------------------------------------------------
Count start flag
------------------------------------------------------*/
union st_tabsr { /* union TABSR */
struct { /* Bit Access */
unsigned char TA0S:1; /* Timer A0 count start flag */
unsigned char TA1S:1; /* Timer A1 count start flag */
unsigned char TA2S:1; /* Timer A2 count start flag */
unsigned char TA3S:1; /* Timer A3 count start flag */
unsigned char TA4S:1; /* Timer A4 count start flag */
unsigned char TB0S:1; /* Timer B0 count start flag */
unsigned char TB1S:1; /* Timer B1 count start flag */
unsigned char TB2S:1; /* Timer B2 count start flag */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /*UART2 transmit/receive control register 1 */
/*------------------------------------------------------
Clock prescaler reset flag
------------------------------------------------------*/
union st_cpsrf { /* union CPSRF */
struct { /* Bit Access */
unsigned char :1; /* */
unsigned char :1; /* */
unsigned char :1; /* */
unsigned char :1; /* */
unsigned char :1; /* */
unsigned char :1; /* */
unsigned char :1; /* */
unsigned char CPSR:1; /* Clock prescaler reset flag */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /* Watchdog timer start register */
/*------------------------------------------------------
One-shot start flag
------------------------------------------------------*/
union st_onsf { /* union ONSF */
struct { /* Bit Access */
unsigned char TA0OS:1; /* Timer A0 one-shot start flag */
unsigned char TA1OS:1; /* Timer A1 one-shot start flag */
unsigned char TA2OS:1; /* Timer A2 one-shot start flag */
unsigned char TA3OS:1; /* Timer A3 one-shot start flag */
unsigned char TA4OS:1; /* Timer A4 one-shot start flag */
unsigned char :1; /* */
unsigned char TA0TGL:1; /* Timer A0 event/trigger select bit */
unsigned char TA0TGH:1; /* Timer A0 event/trigger select bit */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /*UART2 transmit/receive control register 1 */
/*------------------------------------------------------
Trigger select register
------------------------------------------------------*/
union st_trgsr { /* union TRGSR */
struct { /* Bit Access */
unsigned char TA1TGL:1; /* Timer A1 event/trigger select bit */
unsigned char TA1TGH:1; /* Timer A1 event/trigger select bit */
unsigned char TA2TGL:1; /* Timer A2 event/trigger select bit */
unsigned char TA2TGH:1; /* Timer A2 event/trigger select bit */
unsigned char TA3TGL:1; /* Timer A3 event/trigger select bit */
unsigned char TA3TGH:1; /* Timer A3 event/trigger select bit */
unsigned char TA4TGL:1; /* Timer A4 event/trigger select bit */
unsigned char TA4TGH:1; /* Timer A4 event/trigger select bit */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /*UART2 transmit/receive control register 1 */
#if 0
/*------------------------------------------------------
Timer mode registers
------------------------------------------------------*/
union st_tmr {
struct{
unsigned char TMOD0:1; /* Operation mode select bit */
unsigned char TMOD1:1; /* Operation mode select bit */
unsigned char MR0 :1;
unsigned char MR1 :1;
unsigned char MR2 :1;
unsigned char MR3 :1;
unsigned char TCK0 :1; /* Count source select bit */
unsigned char TCK1 :1; /* Count source select bit */
}BIT;
unsigned char BYTE;
};
#endif
/*------------------------------------------------------
UARTi transmit/receive control register 1
------------------------------------------------------*/
union st_u0c1 { /* union U0C1 */
struct { /* Bit Access */
unsigned char TE:1; /* Transmit enable bit */
unsigned char TI:1; /* Transmit buffer empty flag */
unsigned char RE:1; /* Receive enable bit */
unsigned char RI:1; /* Receive complete flag */
unsigned char :1; /* Nothing Assigned */
unsigned char :1; /* Nothing Assigned */
unsigned char :1; /* Nothing Assigned */
unsigned char :1; /* Nothing Assigned */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /*UART0 transmit/receive control register 1 */
union st_u1c1 { /* union U0C1 */
struct { /* Bit Access */
unsigned char TE:1; /* Transmit enable bit */
unsigned char TI:1; /* Transmit buffer empty flag */
unsigned char RE:1; /* Receive enable bit */
unsigned char RI:1; /* Receive complete flag */
unsigned char :1; /* */
unsigned char :1; /* */
unsigned char :1; /* */
unsigned char :1; /* */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /*UART1 transmit/receive control register 1 */
/*------------------------------------------------------
UART transmit/receive control register 2
------------------------------------------------------*/
union st_ucon { /* union UCON */
struct { /* Bit Access */
unsigned char U0IRS :1; /* UART0 transmit interrupt cause select bit*/
unsigned char U1IRS :1; /* UART1 transmit interrupt cause select bit*/
unsigned char U0RRM :1; /* UART0 continuous receive mode enable bit */
unsigned char U1RRM :1; /* UART1 continuous receive mode enable bit */
unsigned char CLKMD0:1; /* CLK/CLKS select bit 0 */
unsigned char CLKMD1:1; /* CLK/CLKS select bit 1 */
unsigned char :1; /* */
unsigned char :1; /* */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /*UART transmit/receive control register 2 */
/*------------------------------------------------------
Flash memory control register 1
------------------------------------------------------*/
union st_fmr1 { /* union FMR1 */
struct { /* Bit Access */
unsigned char :1; /* */
unsigned char :1; /* */
unsigned char :1; /* */
unsigned char FMR13:1; /* Flash memory power supply-OFF bit*/
unsigned char :1; /* */
unsigned char :1; /* */
unsigned char :1; /* */
unsigned char :1; /* */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /* Flash memory control register */
/*------------------------------------------------------
Flash memory control register 0
------------------------------------------------------*/
union st_fmr0 { /* union FMR0 */
struct { /* Bit Access */
unsigned char FMR00:1; /* RY/BY~ status bit */
unsigned char FMR01:1; /* CPU rewrite mode select bit */
unsigned char FMR02:1; /* Lock bit disable bit */
unsigned char FMR03:1; /* Flash memory reset bit */
unsigned char :1;
unsigned char FMR05:1; /* User ROM area select bit */
unsigned char :1;
unsigned char :1; /* */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /* Flash memory control register */
/*------------------------------------------------------
A/D control register 2
------------------------------------------------------*/
union st_adcon2 { /* union ADCON2 */
struct { /* Bit Access */
unsigned char SMP:1; /* A/D conversion method select bit */
unsigned char :1; /* Reserved bit (Always set to 0 ) */
unsigned char :1; /* Reserved bit (Always set to 0 ) */
unsigned char :1; /* Reserved bit (Always set to 0 ) */
unsigned char :1; /* Nothing Assigned. */
unsigned char :1; /* Nothing Assigned. */
unsigned char :1; /* Nothing Assigned. */
unsigned char :1; /* Nothing Assigned. */
} BIT;
unsigned char BYTE; /* Byte Access */
};
/*------------------------------------------------------
A/D control register 0
------------------------------------------------------*/
union st_adcon0 { /* union ADCON0 */
struct { /* Bit Access */
unsigned char CH0 :1; /* Analog input pin select bit */
unsigned char CH1 :1; /* Analog input pin select bit */
unsigned char CH2 :1; /* Analog input pin select bit */
unsigned char MD0 :1; /* A/D operation mode select bit 0 */
unsigned char MD1 :1; /* A/D operation mode select bit 0 */
unsigned char TRG :1; /* Trigger select bit */
unsigned char ADST:1; /* A/D conversion start flag */
unsigned char CKS0:1; /* Frequency select bit 0 */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /*A/D control register 0 */
/*------------------------------------------------------
A/D control register 1
------------------------------------------------------*/
union st_adcon1 { /* union ADCON1 */
struct { /* Bit Access */
unsigned char SCAN0:1; /* A/D sweep pin select bit */
unsigned char SCAN1:1; /* A/D sweep pin select bit */
unsigned char MD2 :1; /* A/D operation mode select bit 1 */
unsigned char BITS :1; /* 8/10-bit mode select bit */
unsigned char CKS1 :1; /* Frequency select bit 1 */
unsigned char VCUT :1; /* Vref connect bit */
unsigned char OPA0 :1; /* External op-amp connection mode bit */
unsigned char OPA1 :1; /* External op-amp connection mode bit */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /*A-D control register 1 */
/*------------------------------------------------------
D/A control register
------------------------------------------------------*/
union st_dacon{ /* union DACON */
struct { /* Bit Access */
unsigned char DA0E :1; /* D/A0 output enable bit */
unsigned char DA1E :1; /* D/A1 output enable bit */
unsigned char :1; /* Nothing Assigned */
unsigned char :1; /* Nothing Assigned */
unsigned char :1; /* Nothing Assigned */
unsigned char :1; /* Nothing Assigned */
unsigned char :1; /* Nothing Assigned */
unsigned char :1; /* Nothing Assigned */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /* D/A control register */
/*------------------------------------------------------
Port P0 register
------------------------------------------------------*/
union st_p0 { /* union P0 */
struct { /* Bit Access */
unsigned char P0_0:1; /* Port P00 register */
unsigned char P0_1:1; /* Port P01 register */
unsigned char P0_2:1; /* Port P02 register */
unsigned char P0_3:1; /* Port P03 register */
unsigned char P0_4:1; /* Port P04 register */
unsigned char P0_5:1; /* Port P05 register */
unsigned char P0_6:1; /* Port P06 register */
unsigned char P0_7:1; /* Port P07 register */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /* */
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