📄 iodefine.h
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unsigned short WORD; /* Word Access */
};
union st_ad1 { /* A/D register 1 16 bit */
struct{
unsigned char AD1L; /* A/D register 1 low 8 bit */
unsigned char AD1H; /* A/D register 1 high 8 bit */
} BYTE; /* Byte access */
unsigned short WORD; /* Word Access */
};
union st_ad2 { /* A/D register 2 16 bit */
struct{
unsigned char AD2L; /* A/D register 2 low 8 bit */
unsigned char AD2H; /* A/D register 2 high 8 bit */
} BYTE; /* Byte access */
unsigned short WORD; /* Word Access */
};
union st_ad3 { /* A/D register 3 16 bit */
struct{
unsigned char AD3L; /* A/D register 3 low 8 bit */
unsigned char AD3H; /* A/D register 3 high 8 bit */
} BYTE; /* Byte access */
unsigned short WORD; /* Word Access */
};
union st_ad4 { /* A/D register 4 16 bit */
struct{
unsigned char AD4L; /* A/D register 4 low 8 bit */
unsigned char AD4H; /* A/D register 4 high 8 bit */
} BYTE; /* Byte access */
unsigned short WORD; /* Word Access */
};
union st_ad5 { /* A/D register 5 16 bit */
struct{
unsigned char AD5L; /* A/D register 5 low 8 bit */
unsigned char AD5H; /* A/D register 5 high 8 bit */
} BYTE; /* Byte access */
unsigned short WORD; /* Word Access */
};
union st_ad6 { /* A/D register 6 16 bit */
struct{
unsigned char AD6L; /* A/D register 6 low 8 bit */
unsigned char AD6H; /* A/D register 6 high 8 bit */
} BYTE; /* Byte access */
unsigned short WORD; /* Word Access */
};
union st_ad7 { /* A/D register 7 16 bit */
struct{
unsigned char AD7L; /* A/D register 7 low 8 bit */
unsigned char AD7H; /* A/D register 7 high 8 bit */
} BYTE; /* Byte access */
unsigned short WORD; /* Word Access */
};
union st_dm0con { /* DMA0 control register union */
struct{
unsigned char DMBIT:1; /* Transfer unit bit select bit */
unsigned char DMASL:1; /* Repeat transfer mode select bit */
unsigned char DMAS :1; /* DMA request bit */
unsigned char DMAE :1; /* DMA enable bit */
unsigned char DSD :1; /* Source address direction select bit */
unsigned char DAD :1; /* Destination address direction select bit */
unsigned char :1;
unsigned char :1;
}BIT;
unsigned char BYTE;
};
union st_dm1con { /* DMA1 control register union */
struct{
unsigned char DMBIT:1; /* Transfer unit bit select bit */
unsigned char DMASL:1; /* Repeat transfer mode select bit */
unsigned char DMAS :1; /* DMA request bit */
unsigned char DMAE :1; /* DMA enable bit */
unsigned char DSD :1; /* Source address direction select bit */
unsigned char DAD :1; /* Destination address direction select bit */
unsigned char :1;
unsigned char :1;
}BIT;
unsigned char BYTE;
};
union st_dm0sl { /* DMAi request cause select registers */
struct{
unsigned char DSEL0:1;/* DMA request cause select bit */
unsigned char DSEL1:1;/* DMA request cause select bit */
unsigned char DSEL2:1;/* DMA request cause select bit */
unsigned char DSEL3:1;/* DMA request cause select bit */
unsigned char :1;
unsigned char :1;
unsigned char DMS :1;/* DMA request cause expansion bit */
unsigned char DSR :1;/* Software DMA request bit */
}BIT;
unsigned char BYTE;
};
union st_dm1sl { /* DMAi request cause select registers */
struct{
unsigned char DSEL0:1; /* DMA request cause select bit */
unsigned char DSEL1:1; /* DMA request cause select bit */
unsigned char DSEL2:1; /* DMA request cause select bit */
unsigned char DSEL3:1; /* DMA request cause select bit */
unsigned char :1;
unsigned char :1;
unsigned char DMS :1; /* DMA request cause expansion bit */
unsigned char DSR :1; /* Software DMA request bit */
}BIT;
unsigned char BYTE;
};
union st_icr { /* interrupt control registers */
struct{
unsigned char ILVL0:1; /* Interrupt priority level select bit */
unsigned char ILVL1:1; /* Interrupt priority level select bit */
unsigned char ILVL2:1; /* Interrupt priority level select bit */
unsigned char IR :1; /* Interrupt request bit */
unsigned char POL :1; /* Polarity select bit */
unsigned char LVS :1;
unsigned char :1; /* Nothing assigned */
unsigned char :1; /* Nothing assigned */
}BIT;
unsigned char BYTE;
};
union st_tbsr { /* union tbsr */
struct { /* Bit Access */
unsigned char :1; /* Nothing Assigned */
unsigned char :1; /* Nothing Assigned */
unsigned char :1; /* Nothing Assigned */
unsigned char :1; /* Nothing Assigned */
unsigned char :1; /* Nothing Assigned */
unsigned char TB3S:1; /* Timer B3 count start flag */
unsigned char TB4S:1; /* Timer B4 count start flag */
unsigned char TB5S:1; /* Timer B5 count start flag */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /* Timer B3,4,5 Count start flag */
/*------------------------------------------------------
Three-phase PWM control regester 0
------------------------------------------------------*/
union st_invc0 { /* union invc0 */
struct { /* Bit Access */
unsigned char INV00:1;/* Effective interrupt output polarity select bit */
unsigned char INV01:1;/* Effective interrupt output specification bit */
unsigned char INV02:1;/* Mode select bit */
unsigned char INV03:1;/* Output control bit */
unsigned char INV04:1;/* Positive and negative phases concurrent L output disable function enable bit */
unsigned char INV05:1;/* Positive and negative phases concurrent L output detect flag */
unsigned char INV06:1;/* Modulation mode select bit */
unsigned char INV07:1;/* Software trigger bit */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /* */
/*------------------------------------------------------
Three-phase PWM control regester 1
------------------------------------------------------*/
union st_invc1 { /* union invc1 */
struct { /* Bit Access */
unsigned char INV00:1;/* Timer Ai start trigger signal select bit */
unsigned char INV11:1;/* Timer A1-1,A2-1,A4-1 control bit */
unsigned char INV12:1;/* Short circuit timer count source select bit*/
unsigned char :1;/* Nothing Assigned */
unsigned char :1;/* Reserved bit (always 0) */
unsigned char :1;/* Nothing Assigned */
unsigned char :1;/* Nothing Assigned */
unsigned char :1;/* Nothing Assigned */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /* */
/*------------------------------------------------------
Three-phase output buffer register 0
------------------------------------------------------*/
union st_idb0 { /* union idb0 */
struct { /* Bit Access */
unsigned char DU0 :1;/* U phase output buffer 0 */
unsigned char DUB0:1;/* U~ phase output buffer 0 */
unsigned char DV0 :1;/* V phase output buffer 0 */
unsigned char DVB0:1;/* V~ phase output buffer 0 */
unsigned char DW0 :1;/* W phase output buffer 0 */
unsigned char DWB0:1;/* W~ phase output buffer 0 */
unsigned char :1;/* Nothing Assigned */
unsigned char :1;/* Nothing Assigned */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /* */
/*------------------------------------------------------
Three-phase output buffer register 1
------------------------------------------------------*/
union st_idb1 { /* union idb1 */
struct { /* Bit Access */
unsigned char DU1 :1;/* U phase output buffer 1 */
unsigned char DUB1:1;/* U~ phase output buffer 1 */
unsigned char DV1 :1;/* V phase output buffer 1 */
unsigned char DVB1:1;/* V~ phase output buffer 1 */
unsigned char DW1 :1;/* W phase output buffer 1 */
unsigned char DWB1:1;/* W~ phase output buffer 1 */
unsigned char :1;/* Nothing Assigned */
unsigned char :1;/* Nothing Assigned */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /* */
/*------------------------------------------------------
Timer mode registers
------------------------------------------------------*/
union st_tmr { /* union tmr */
struct { /* Bit Access */
unsigned char TMOD0:1; /* Operation mode select bit */
unsigned char TMOD1:1; /* Operation mode select bit */
unsigned char MR0 :1; /* Pulse output function select bit */
unsigned char MR1 :1; /* External trigger select bit */
unsigned char MR2 :1; /* Trigger select bit */
unsigned char MR3 :1; /* Must always be "0" in one-shot timer*/
unsigned char TCK0 :1; /* Count source select bit */
unsigned char TCK1 :1; /* Count source select bit */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
};
/*------------------------------------------------------
Interrupt request cause select register
-----------------------------------------------------*/
union st_ifsr { /* union IFSR */
struct { /* Bit Access */
unsigned char IFSR0:1; /* INT0~ interrupt polarity switching bit */
unsigned char IFSR1:1; /* INT1~ interrupt polarity switching bit */
unsigned char IFSR2:1; /* INT2~ interrupt polarity switching bit */
unsigned char IFSR3:1; /* INT3~ interrupt polarity switching bit */
unsigned char IFSR4:1; /* INT4~ interrupt polarity switching bit */
unsigned char IFSR5:1; /* INT5~ interrupt polarity switching bit */
unsigned char IFSR6:1; /* Interrupt request cause select bit */
unsigned char IFSR7:1; /* Interrupt request cause select bit */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /* */
/*------------------------------------------------------
SI/O3 control registers
------------------------------------------------------*/
union st_s3c { /* union S3C */
struct { /* Bit Access */
unsigned char SM30:1; /* Internal synchronous clock select bit */
unsigned char SM31:1; /* Internal synchronous clock select bit */
unsigned char SM32:1; /* Sout3 output disable bit */
unsigned char SM33:1; /* SI/O3 port select bit */
unsigned char :1;
unsigned char SM35:1; /* Transfer direction select bit */
unsigned char SM36:1; /* Synchronous clock select bit */
unsigned char SM37:1; /* Sout3 initial value set bit */
} BIT; /* */
unsigned char BYTE; /* Byte Access */
}; /* */
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