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📄 iodefine.h

📁 M16C单片机功率控制源码
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/****************************************************************
KPIT Cummins Infosystems Ltd, Pune, India.  27-June-2005.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

*****************************************************************/
/****************************************************************/
/*      M16C/60 62A Include File                                */
/****************************************************************/


/*------------------------------------------------------
    Processor mode register 0
------------------------------------------------------*/
union st_pm0 {               /* union PM0    	   					*/
  struct {             		 /* Bit  Access 		   				*/
	 unsigned char 	PM0_0:1; /* Processor mode bit 0 				*/
	 unsigned char 	PM0_1:1; /* Processor mode bit 1 				*/
	 unsigned char 	PM0_2:1; /* R/W mode select bit  				*/
	 unsigned char 	PM0_3:1; /* Software reset bit					*/
	 unsigned char 	PM0_4:1; /* Multiplexed bus space select bit 0	*/
	 unsigned char 	PM0_5:1; /* Multiplexed bus space select bit 1	*/
	 unsigned char 	PM0_6:1; /* Port P40 to P43 function select bit */
	 unsigned char 	PM0_7:1; /* BCLK output disable bit		      	*/
  } BIT;   		     		 /*        						    	*/
	unsigned  char BYTE;     /*  Byte Access 						*/
};                           /* 						            */

/*------------------------------------------------------
    Processor mode register 1
------------------------------------------------------*/
union st_pm1 {              /* union PM1    	   					*/
  struct {            		/* Bit  Access 		   					*/
	 unsigned char 		:1; /* Reserved bit 						*/
	 unsigned char 		:1; /* Nothing assigned 					*/
	 unsigned char 		:1; /* Nothing assigned  					*/
	 unsigned char PM1_3:1; /* PM13(Internal reserved area expansion bit 0*/
	 unsigned char 		:1; /* Reserved bit 						*/
	 unsigned char 		:1; /* Reserved bit 						*/
	 unsigned char 		:1; /* Reserved bit  						*/
	 unsigned char PM1_7:1; /* PM17 - Wait bit				    	*/
  } BIT;   		    		/*        						    	*/
	 unsigned char BYTE;    /*  Byte Access 						*/
};                          /* 						            	*/

/*------------------------------------------------------
    System clock control register 0
------------------------------------------------------*/
union st_cm0 {               /* union CM0    	   					*/
  struct {             		 /* Bit  Access 		   				*/
	 unsigned char 	CM0_0:1; /* Clock output function select bit 	*/
	 unsigned char 	CM0_1:1; /* Clock output function select bit 	*/
	 unsigned char 	CM0_2:1; /* WAIT peripheral function clock stop bit */
	 unsigned char 	CM0_3:1; /* Xcin-Xcout drive capacity select bit*/
	 unsigned char 	CM0_4:1; /* Port Xc select bit 					*/
	 unsigned char 	CM0_5:1; /* Main clock stop bit					*/
	 unsigned char 	CM0_6:1; /* Main clock division select bit 0 	*/
	 unsigned char 	CM0_7:1; /* System clock select bit 			*/
  } BIT;   		     		 /*        						    	*/
	unsigned char BYTE;      /*  Byte Access 						*/
};                           /* system clock control register  0    */


/*------------------------------------------------------
    System clock control register 1
------------------------------------------------------*/
union st_cm1 {               /* union CM1    	   					*/
  struct {             		 /* Bit  Access 		   				*/
	 unsigned char 	CM1_0:1; /* All clock stop control bit 			*/
	 unsigned char 		 :1; /* Reserved bit always set to 0		*/
	 unsigned char 	 	 :1; /* Reserved bit always set to 0		*/
	 unsigned char 		 :1; /* Reserved bit always set to 0		*/
	 unsigned char 		 :1; /* Reserved bit always set to 0		*/
	 unsigned char 	CM1_5:1; /* Xin-Xouts drive capacity select bit */
	 unsigned char 	CM1_6:1; /* Main clock division select bit 1 	*/
	 unsigned char 	CM1_7:1; /* Main clock division select bit 1 	*/
  } BIT;   		     		 /*        						    	*/
	unsigned char BYTE;      /*  Byte Access 						*/
};                           /* system clock control register 1     */


/*------------------------------------------------------
    Chip select control register
------------------------------------------------------*/
union st_csr {               /* union CSR    	   					*/
   struct {             	 /* Bit  Access 		   				*/
	 unsigned char	CS0 :1;  /* CS0~ output enable bit				*/
	 unsigned char	CS1 :1;  /* CS1~ output enable bit 				*/
	 unsigned char	CS2 :1;  /* CS2~ output enable bit 				*/
	 unsigned char	CS3 :1;  /* CS3~ output enable bit 				*/
	 unsigned char	CS0W:1;  /* CS0~ wait bit 						*/
	 unsigned char	CS1W:1;  /* CS1~ wait bit 						*/
	 unsigned char	CS2W:1;  /* CS2~ wait bit 						*/
	 unsigned char	CS3W:1;  /* CS3~ wait bit 						*/
   } BIT;   		         /*        						    	*/
	 unsigned char BYTE;     /* Byte Access 						*/
};                           /* Chip select control register		*/

/*------------------------------------------------------
    Address match interrupt enable register
------------------------------------------------------*/
union st_aier {               /* union AIER    	   					*/
   struct {              	  /* Bit  Access 		   				*/
	 unsigned char 	AIER0:1;  /* Address match interrupt0 enable bit*/
	 unsigned char 	AIER1:1;  /* Address match interrupt1 enable bit*/
	 unsigned char 		 :1;  /* Nothing assigned 					*/
	 unsigned char 		 :1;  /* Nothing assigned 					*/
	 unsigned char 		 :1;  /* Nothing assigned  					*/
	 unsigned char 		 :1;  /* Nothing assigned  					*/
	 unsigned char 	 	 :1;  /* Nothing assigned 					*/
	 unsigned char 		 :1;  /* Nothing assigned  					*/
   } BIT;   		      	  /*       						    	*/
	 unsigned char BYTE;      /* Byte Access 						*/
};                            /* Address match interrupt enable register	*/


/*------------------------------------------------------
   Protect register
-----------------------------------------------------*/
union st_prcr {               /* union PRCR    	   					*/
   struct {              	  /* Bit  Access 		   				*/
	 unsigned char 	PRC0:1;   /* Enables writing to system clock control registers 0 & 1 */
	 unsigned char 	PRC1:1;   /* Enables writing to processor mode registers 0 & 1 */
	 unsigned char 	PRC2:1;   /* Enables writing to port P9 direction register & SI/Oi control register(i=3,4)*/
	 unsigned char 		:1;   /* Nothing assigned 					*/
	 unsigned char 		:1;   /* Nothing assigned  					*/
	 unsigned char 		:1;   /* Nothing assigned  					*/
	 unsigned char 	 	:1;   /* Nothing assigned 					*/
	 unsigned char 		:1;   /* Nothing assigned  					*/
   } BIT;   		      	  /*       						    	*/
	 unsigned char BYTE;      /* Byte Access 						*/
};                            /* Protect register					*/

/*------------------------------------------------------
   Watchdog timer control register
-----------------------------------------------------*/
union st_wdc {               /* union WDC    	   					*/
   struct {             	 /* Bit  Access 		   				*/
     unsigned char 	 B0:1; 	 /* High-order bit of watchdog timer	*/
     unsigned char 	 B1:1; 	 /* High-order bit of watchdog timer	*/
     unsigned char 	 B2:1; 	 /* High-order bit of watchdog timer	*/
     unsigned char 	 B3:1;   /* High-order bit of watchdog timer	*/
     unsigned char 	 B4:1; 	 /* High-order bit of watchdog timer	*/
     unsigned char 	 B5:1; 	 /* Reserved bit, must always be 0		*/
     unsigned char 	 B6:1; 	 /* Reserved bit, must always be 0		*/
     unsigned char WDC7:1;   /* Prescaler select bit				*/
   } BIT;   		    	 /*        						    	*/
     unsigned char BYTE;     /*  Byte Access 						*/
};                           /* Watchdog timer control register     */

union st_rmad0 {
   struct{
	unsigned char RMAD0L;     /* Address match interrupt register 0 low  8 bit */
	unsigned char RMAD0M;     /* Address match interrupt register 0 mid  8 bit */
	unsigned char RMAD0H;     /* Address match interrupt register 0 high 8 bit */
	unsigned char NC;         /* non use 									   */
   } BYTE;					  /* Byte access								   */
	unsigned long   DWORD;	  /*	Word Access								   */
};							  /* Address match interrupt register 0 32 bit 	   */


union st_rmad1 {
   struct{
	unsigned char RMAD1L;     /* Address match interrupt register 1 low  8 bit */
	unsigned char RMAD1M;     /* Address match interrupt register 1 mid  8 bit */
	unsigned char RMAD1H;     /* Address match interrupt register 1 high 8 bit */
	unsigned char NC;         /* non use 									   */
   } BYTE;					  /* Byte access								   */
   unsigned long   DWORD;	  /*	Word Access								   */
};							  /* Address match interrupt register 1 32 bit 	   */

union st_sar0 {
   struct{
	unsigned char SAR01;     /* DMA0 source pointer low  8 bit 				 */
	unsigned char SAR0M;     /* DMA0 source pointer mid  8 bit 				 */
	unsigned char SAR0H;     /* DMA0 source pointer high 8 bit 				 */
	unsigned char NC;        /* non use 									 */
   } BYTE;				 	 /* Byte access									 */
   unsigned long   DWORD;	 /*	Word Access									 */
};							 /* DMA0 source pointer 32 bit				 	 */

union st_sar1 {
   struct{
	unsigned char SAR11;     /* DMA1 source pointer low  8 bit 				 */
	unsigned char SAR1M;     /* DMA1 source pointer mid  8 bit 				 */
	unsigned char SAR1H;     /* DMA1 source pointer high 8 bit 				 */
	unsigned char NC;        /* non use 									 */
   } BYTE;					 /* Byte access									 */
   unsigned long   DWORD;	 /* Word Access									 */
};					         /* DMA1 source pointer 32 bit				 	 */

union st_dar0 {				 /* DMA0 destination pointer 32 bit	   			 */
   struct{
	unsigned char DAR01;     /* DMA0 destination pointer low  8 bit  		 */
	unsigned char DAR0M;     /* DMA0 destination pointer mid  8 bit     	 */
	unsigned char DAR0H;     /* DMA0 destination pointer high 8 bit  		 */
	unsigned char NC;        /* non use 							   		 */
   } BYTE;					 /* Byte access						   			 */
    unsigned long DWORD;	 /* Word Access						   			 */
};

union st_dar1 {				  /* DMA1 destination pointer 32 bit			 */
   struct{
	unsigned char DAR11;     /* DMA1 destination pointer low  8 bit			 */
	unsigned char DAR1M;     /* DMA1 destination pointer mid  8 bit			 */
	unsigned char DAR1H;     /* DMA1 destination pointer high 8 bit			 */
	unsigned char NC;        /* non use 									 */
   } BYTE;					 /* Byte access									 */
   unsigned long   DWORD;	 /* Word Access									 */
};

union st_tcr0 {			  	 /* DMA0 transfer counter 16 bit 	 			 */
   struct{
	unsigned char TCR0L;     /* DMA0 transfer counter low  8 bit 			 */
	unsigned char TCR0H;     /* DMA0 transfer counter high 8 bit 			 */
   } BYTE;					 /* Byte access					     			 */
   unsigned short   WORD;	 /* Word Access					     			 */
};

union st_tcr1 {				  /* DMA1 transfer counter 16 bit 	   			 */
   struct{
	unsigned char TCR1L;     /* DMA1 transfer counter low  8 bit   			 */
	unsigned char TCR1H;     /* DMA1 transfer counter high 8 bit   			 */
   } BYTE;					 /* Byte access					       			 */
   unsigned short WORD;	     /* Word Access					       			 */
};


union st_u0tb {				/* UART0 Transmit buffer register 16 bit ; Use "MOV" instruction when writing to this register. */
   struct{
	unsigned char U0TBL;     /* UART0 Transmit buffer register low  8 bit 	 */
	unsigned char U0TBH;     /* UART0 Transmit buffer register high 8 bit 	 */
   } BYTE;					 /* Byte access					   				 */
   unsigned short   WORD;	 /* Word Access					   				 */
};

union st_u1tb {				 /* UART1 Transmit buffer register 16 bit ; Use "MOV" instruction when writing to this register. */
   struct{
	unsigned char U1TBL;     /* UART1 Transmit buffer register low  8 bit    */
	unsigned char U1TBH;     /* UART1 Transmit buffer register high 8 bit    */
   } BYTE;					 /* Byte access					   				 */
   unsigned short   WORD;	 /* Word Access					   				 */
};

union st_u2tb {				 /* UART2 Transmit buffer register 16 bit ; Use "MOV" instruction when writing to this register. */
   struct{
	unsigned char U2TBL;     /* UART2 Transmit buffer register low  8 bit 	 */
	unsigned char U2TBH;     /* UART2 Transmit buffer register high 8 bit  	 */
   } BYTE;				 	 /* Byte access					   				 */
   unsigned short   WORD;	 /* Word Access					   				 */
};

union st_crcd {				 /* CRC data register 16 bit     				 */
   struct{
	unsigned char CRCDL;     /* CRC data register low  8 bit 				 */
	unsigned char CRCDH;     /* CRC data register high 8 bit 				 */
   } BYTE;					 /* Byte access					 				 */
   unsigned short   WORD;    /* Word Access					 				 */
};



union st_ad0 {				 /* A/D register 0 16 bit 						*/
   struct{
	unsigned char AD0L;      /* A/D register 0 low  8 bit 					*/
	unsigned char AD0H;      /* A/D register 0 high 8 bit 					*/
   }BYTE;					 /* Byte access					    			*/

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