k9f1g08.c

SMDK2442所有设备的驱动测试程序。运行monitor程序

	int i;
	
	i=0;	
	Uart_Printf("\n\n");
	while(1)
	{   //display menu
	    Uart_Printf("%2d:%s",i,n1G08_func[i][1]);
	    i++;
	    if((int)(n1G08_func[i][0])==0)
	    {
		 Uart_Printf("\n");
		 break;
	    }
	    if((i%4)==0) Uart_Printf("\n");
	}
}
*/

static int NF1G08_EraseBlock(U32 block)
{
    U32 blockPage=(block<<6);
    int i;

    NFConDone_1G08=0;
    rNFCONT|=(1<<9);
    rNFCONT|=(1<<10);
    pISR_NFCON= (unsigned)NFCon_Int_1G08;
    rSRCPND=BIT_NFCON;
    rINTMSK=~(BIT_NFCON);
	
#if BAD_CHECK
    if(NF1G08_IsBadBlock(block))
	return FAIL;
#endif

	#if Nand_FCE 
 		EXT_NF_nFCE_L();
	#else
		NF_nFCE_L();
	#endif
    
	NF_CMD(0x60);   // Erase one block 1st command, Block Addr:A9-A25
	// Address 2-cycle
	NF_ADDR(blockPage&0xff);	    // Page number=0
	NF_ADDR((blockPage>>8)&0xff);   
	


	NF_CLEAR_RB();
	NF_CMD(0xd0);	// Erase one blcok 2nd command
//	NF_DETECT_RB();
       while(NFConDone_1G08==0);
	 rNFCONT&=~(1<<9);
	 rNFCONT&=~(1<<10); // Disable Illegal Access Interrupt
	 if(rNFSTAT&0x8) return FAIL;

	NF_CMD(0x70);   // Read status command

      if (NF_RDDATA()&0x1) // Erase error
      {	

	#if Nand_FCE 
 		EXT_NF_nFCE_H();
	#else
		NF_nFCE_H();
	#endif

	Uart_Printf("[ERASE_ERROR:block#=%d]\n",block);
//	NF8_MarkBadBlock(block);
	return FAIL;
       }
       else 
       {

	#if Nand_FCE 
 		EXT_NF_nFCE_H();
	#else
		NF_nFCE_H();
	#endif
	
       return OK;
       }
}


void __irq NFCon_Int_1G08(void)
{
       NFConDone_1G08=1;
	rINTMSK|=BIT_NFCON;
	ClearPending(BIT_NFCON);
	if(rNFSTAT&0x8) Uart_Printf("Illegal Access is detected!!!\n");
//	else Uart_Printf("RnB is Detected!!!\n"); 
}


static int NF1G08_IsBadBlock(U32 block)
{
       int i;
       unsigned int blockPage;
	U8 data;
    
    
       blockPage=(block<<6);	// For 2'nd cycle I/O[7:5] 
    
	#if Nand_FCE 
 		EXT_NF_nFCE_L();
	#else
		NF_nFCE_L();
	#endif
	
	NF_CLEAR_RB();

       NF_CMD(0x00);	// Read command
       NF_ADDR((2048+0)&0xff);			// 2060 = 0x080c
	NF_ADDR(((2048+0)>>8)&0xff)
       NF_ADDR((blockPage)&0xff);	// A[19:12]
       NF_ADDR((blockPage>>8)&0xff);	// A[27:20]
      
       NF_CMD(0x30);	// 2'nd command
       NF_DETECT_RB();
	   
	
       data=NF_RDDATA();

	#if Nand_FCE 
 		EXT_NF_nFCE_H();
	#else
		NF_nFCE_H();
	#endif    

     if(data!=0xff)
     {
    	Uart_Printf("[block %d has been marked as a bad block(%x)]\n",block,data);
    	return FAIL;
     }
     else
     {
    	return OK;
     }
}


static int NF1G08_MarkBadBlock(U32 block)
{
       int i;
	U32 blockPage=(block<<6);
 
     se8Buf[0]=0x44;
     se8Buf[1]=0xff;    
     se8Buf[2]=0xff;    
     se8Buf[5]=0xff;   // Bad blcok mark=44

	#if Nand_FCE 
 		EXT_NF_nFCE_L();
	#else
		NF_nFCE_L();
	#endif
	
	NF_CMD(0x80);   // Write 1st command
	
	NF_ADDR((1024+0)&0xff);			// 2060 = 0x080c
	NF_ADDR(((1024+0)>>8)&0xff);	// A[10:8]
	NF_ADDR((blockPage)&0xff);	// A[11;18]
	NF_ADDR((blockPage>>8)&0xff);	// A[26:19]
	
	
	NF_WRDATA(se8Buf[0]);	// Write Bad block information

	NF_CLEAR_RB();
	NF_CMD(0x10);   // Write 2nd command
	NF_DETECT_RB();

	NF_CMD(0x70);
  
	for(i=0;i<64;i++)
      {
	   NF_WRDATA(se8Buf[i]);	// Write spare array
      }

	NF_CLEAR_RB();
	NF_CMD(0x10);   // Write 2nd command
	NF_DETECT_RB();

	NF_CMD(0x70);
    
	for(i=0;i<3;i++);  //twhr=60ns////??????
    
      if (NF_RDDATA()&0x1) // Spare arrray write error
      {	
    	#if Nand_FCE 
 		EXT_NF_nFCE_H();
	#else
		NF_nFCE_H();
	#endif
	
    	Uart_Printf("[Program error is occurred but ignored]\n");
       }
      else 
      {
    	#if Nand_FCE 
 		EXT_NF_nFCE_H();
	#else
		NF_nFCE_H();
	#endif
	
      }

	Uart_Printf("[block #%d is marked as a bad block]\n",block);
       return OK;
}

static int NF1G08_ReadPage(U32 block,U32 page,U8 *buffer)
{
       int i;
       unsigned int blockPage;
	U32 Mecc, Secc;
	U8 *bufPt=buffer;
	    
       blockPage=(block<<6)+page;
	NF_RSTECC();    // Initialize ECC
	NF_MECC_UnLock();
    
	#if Nand_FCE 
 		EXT_NF_nFCE_L();
	#else
		NF_nFCE_L();
	#endif   

	NF_CLEAR_RB();
	NF_CMD(0x00);	// Read command
       NF_ADDR(0); 	// Column (A[7:0]) = 0
       NF_ADDR(0);		// A[11:8]
       NF_ADDR((blockPage)&0xff);	// A[19:12]
       NF_ADDR((blockPage>>8)&0xff);	// A[27:20]
      
       NF_CMD(0x30);	// 2'nd command
       NF_DETECT_RB();
	
      #if TRANS_MODE==C_LANG
	    for(i=0;i<2048;i++) {
	    	*bufPt++=NF_RDDATA8();	// Read one page
	    }
      #elif TRANS_MODE==DMA
		// Nand to memory dma setting
	    rSRCPND=BIT_DMA0;	// Init DMA src pending.
	    rDISRC0=NFDATA; 	// Nand flash data register
	    rDISRCC0=(0<<1) | (1<<0); //arc=AHB,src_addr=fix
	    rDIDST0=(unsigned)bufPt;
	    rDIDSTC0=(0<<1) | (0<<0); //dst=AHB,dst_addr=inc;
	    rDCON0=(1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(0<<23)|(1<<22)|(2<<20)|(2048/4/4);
		//Handshake,AHB,interrupt,(4-burst),whole,S/W,no_autoreload,word,count=128;

		// DMA on and start.
	    rDMASKTRIG0=(1<<1)|(1<<0);

		while(!(rSRCPND & BIT_DMA0));	// Wait until Dma transfer is done.
		
	    rSRCPND=BIT_DMA0;

      #endif

  /*  
	  NF_MECC_Lock();
	  
	  rNFMECCD0=NF_RDDATA();
	  
	  NF_nFCE_H();	  
	  
	  if ((rNFESTAT0&0x3) == 0x0) 	  return OK;
	  else   return FAIL;
*/

	 NF_MECC_Lock();

//	 NF_SECC_UnLock();
        NF1G08_Spare_Data[0]=NF_RDDATA8();
	 Mecc=NF_RDDATA();
	 rNFMECCD0=((Mecc&0xff00)<<8)|(Mecc&0xff);
	 rNFMECCD1=((Mecc&0xff000000)>>8)|((Mecc&0xff0000)>>16);
	
//	 NF_SECC_Lock();
	 NF1G08_Spare_Data[1]=(U8)(Mecc&0xff);
	 NF1G08_Spare_Data[2]=(U8)((Mecc>>8) & 0xff);
	 NF1G08_Spare_Data[3]=(U8)((Mecc>>16) & 0xff);
	 NF1G08_Spare_Data[4]=(U8)((Mecc>>24) & 0xff);

	 for(i=5;i<64;i++) {
    	NF1G08_Spare_Data[i]=NF_RDDATA8();	// Read spare array with 4byte width
       }
/*	 NF_RDDATA();  // read 4~7
	 Secc=NF_RDDATA();
	 rNFSECCD=((Secc&0xff00)<<8)|(Secc&0xff);
	 NF8_Spare_Data[8]=Secc&0xff;
	 NF8_Spare_Data[9]=(Secc&0xff00)>>8;
	 NF8_Spare_Data[10]=(Secc&0xff0000)>>16;
	 NF8_Spare_Data[11]=(Secc&0xff000000)>>24;
	 */
	 
	 #if Nand_FCE 
 		EXT_NF_nFCE_H();
	#else
		NF_nFCE_H();
	#endif    

	 if ((rNFESTAT0&0x3) == 0x0){
	       Uart_Printf("ECC OK!\n");
		return OK;
	 }
	 else {
		Uart_Printf("ECC FAIL!\n");
	       return FAIL;
	 }


}


static int NF1G08_WritePage(U32 block,U32 page,U8 *buffer)
{
    int i;
	U32 blockPage, Mecc, Secc;
	U8 *bufPt=buffer;

	NFConDone_1G08=0;
       rNFCONT|=(1<<9);
       rNFCONT|=(1<<10);
       pISR_NFCON= (unsigned)NFCon_Int_1G08;
       rSRCPND=BIT_NFCON;
       rINTMSK=~(BIT_NFCON);
	  
	NF_RSTECC();    // Initialize ECC
       NF_MECC_UnLock();
	blockPage=(block<<6)+page;

	#if Nand_FCE 
 		EXT_NF_nFCE_L();
	#else
		NF_nFCE_L();
	#endif
	
	NF_CMD(0x80);   // Write 1st command
	NF_ADDR(0); 	// Column (A[7:0]) = 0
	NF_ADDR(0); 	// A[11:8]
	NF_ADDR((blockPage)&0xff);	// A[19:12]
	NF_ADDR((blockPage>>8)&0xff);	// A[27:20]
	
	
#if TRANS_MODE==C_LANG
     
	for(i=0;i<2048;i++) {
		NF_WRDATA8(*bufPt++);	// Write one page to NFM from buffer
    }
#elif TRANS_MODE==DMA
      
	// Memory to Nand dma setting
	rSRCPND=BIT_DMA0;	// Init DMA src pending.
	rDISRC0=(unsigned)bufPt; 	// Nand flash data register
	rDISRCC0=(0<<1) | (0<<0); //arc=AHB,src_addr=inc
	rDIDST0=NFDATA;
	rDIDSTC0=(0<<1) | (1<<0); //dst=AHB,dst_addr=fix;
	rDCON0=(1<<31)|(1<<30)|(1<<29)|(0<<28)|(1<<27)|(0<<23)|(1<<22)|(2<<20)|(2048/4);
	//  only unit transfer in writing!!!!
	//Handshake,AHB,interrupt,(unit),whole,S/W,no_autoreload,word,count=128;
	
	// DMA on and start.
	rDMASKTRIG0=(1<<1)|(1<<0);
	
	while(!(rSRCPND & BIT_DMA0));	// Wait until Dma transfer is done.
	rSRCPND=BIT_DMA0;	
#endif
/*
      NF_MECC_Lock();
// Get ECC data.
	// Spare data for 8bit
	// byte  0   1    2    3    4   5
	// ecc  [0]  [1]  [2]  [3]  x   [Bad marking]
	Mecc = rNFMECC0;
	se8Buf[0]=(U8)(Mecc&0xff);
	se8Buf[1]=(U8)((Mecc>>8) & 0xff);
	se8Buf[2]=(U8)((Mecc>>16) & 0xff);
	se8Buf[3]=(U8)((Mecc>>24) & 0xff);
	se8Buf[5]=0xffff;		// Marking good block

	//Write extra data(ECC, bad marking)
	for(i=0;i<16;i++) {
		NF_WRDATA8(se8Buf[i]);	// Write spare array(ECC and Mark)
		NF8_Spare_Data[i]=se8Buf[i];
    }  

 	NF_CLEAR_RB();
	NF_CMD(0x10);	 // Write 2nd command
	NF_DETECT_RB();

	NF_CMD(0x70);   // Read status command   
    
	for(i=0;i<3;i++);  //twhr=60ns
     
    if (NF_RDDATA()&0x1) {// Page write error
    	
		Uart_Printf("[PROGRAM_ERROR:block#=%d]\n",block);
		NF8_MarkBadBlock(block);
		 NF_nFCE_H();
		return FAIL;
    } else {
    	   NF_nFCE_H();
	  return OK;
	   
	}
*/

       NF_MECC_Lock();
	// Get ECC data.
	// Spare data for 8bit
	// byte  0                  1    2     3     4          5               6      7            8         9
	// ecc  [Bad marking] [0]  [1]  [2]  [3]    x                       SECC0  SECC1
	Mecc = rNFMECC0;

	se8Buf[0]=0xff;
	se8Buf[1]=(U8)(Mecc&0xff);
	se8Buf[2]=(U8)((Mecc>>8) & 0xff);
	se8Buf[3]=(U8)((Mecc>>16) & 0xff);
	se8Buf[4]=(U8)((Mecc>>24) & 0xff);
			// Marking good block

//	NF_SECC_UnLock();
	//Write extra data(ECC, bad marking)
	for(i=0;i<5;i++) {
		NF_WRDATA8(se8Buf[i]);	// Write spare array(Main ECC)
		NF1G08_Spare_Data[i]=se8Buf[i];
    	}  
/*      NF_SECC_Lock(); 
	Secc=rNFSECC; 
	se8Buf[8]=(U8)(Secc&0xff);
	se8Buf[9]=(U8)((Secc>>8) & 0xff);
	*/
	for(i=5;i<64;i++) {
		NF_WRDATA8(se8Buf[i]);  // Write spare array(Spare ECC and Mark)
		NF1G08_Spare_Data[i]=se8Buf[i];
	}  
 	NF_CLEAR_RB();
	NF_CMD(0x10);	 // Write 2nd command
//	NF_DETECT_RB();
	while(NFConDone_1G08==0);
	 rNFCONT&=~(1<<9);
	 rNFCONT&=~(1<<10); // Disable Illegal Access Interrupt
	 if(rNFSTAT&0x8) return FAIL;

	NF_CMD(0x70);   // Read status command   
    
	for(i=0;i<3;i++);  //twhr=60ns
    
       if (NF_RDDATA()&0x1) {// Page write error
    	       #if Nand_FCE 
 			EXT_NF_nFCE_H();
		#else
			NF_nFCE_H();
		#endif
	
		Uart_Printf("[PROGRAM_ERROR:block#=%d]\n",block);
		NF1G08_MarkBadBlock(block);
		return FAIL;
       } else {
    	      #if Nand_FCE 
 			EXT_NF_nFCE_H();
		#else
			NF_nFCE_H();
		#endif
	      return OK;
	}

}


static U16 NF1G08_CheckId(void)
{
    int i;
	U16 id, id4th;

	
	#if Nand_FCE 
 		EXT_NF_nFCE_L();
	#else
		NF_nFCE_L();
	#endif
	
      	NF_CMD(0x90);
	NF_ADDR(0x0);
	for (i=0; i<10; i++);
	Uart_Printf("11NFSTAT: 0x%x\n", rNFSTAT);
       id=NF_RDDATA8()<<8;	// Maker code 0xec
       id|=NF_RDDATA8();	// Devide code(K9S1208V:0x76), (K9K2G16U0M:0xca)

	#if Nand_FCE 
 		EXT_NF_nFCE_H();
	#else
		NF_nFCE_H();
	#endif
    
       return id;
}


/*void Nand_Reset(void)
{
    int i;
   
	NF_nFCE_L();

	NF_CLEAR_RB();
	NF_CMD(0xFF);	//reset command
	for(i=0;i<10;i++);  //tWB = 100ns. //??????
	NF_DETECT_RB();
	
	NF_nFCE_H();

}
*/
static void NF1G08_Init(void)
{
	// for S3C2442

	rNFCONF = (TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4)|(0<<0);	
	// TACLS		[14:12]	CLE&ALE duration = HCLK*TACLS.
	// TWRPH0		[10:8]	TWRPH0 duration = HCLK*(TWRPH0+1)
	// TWRPH1		[6:4]	TWRPH1 duration = HCLK*(TWRPH1+1)
	// AdvFlash(R)	[3]		Advanced NAND, 0:256/512, 1:1024/2048
	// PageSize(R)	[2]		NAND memory page size
	//						when [3]==0, 0:256, 1:512 bytes/page.
	//						when [3]==1, 0:1024, 1:2048 bytes/page.
	// AddrCycle(R)	[1]		NAND flash addr size
	//						when [3]==0, 0:3-addr, 1:4-addr.
	//						when [3]==1, 0:4-addr, 1:5-addr.
	// BusWidth(R/W) [0]	NAND bus width. 0:8-bit, 1:16-bit.
	
	rNFCONT = (0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0);
	// Lock-tight	[13]	0:Disable lock, 1:Enable lock.
	// Soft Lock	[12]	0:Disable lock, 1:Enable lock.
	// EnablillegalAcINT[10]	Illegal access interupt control. 0:Disable, 1:Enable
	// EnbRnBINT	[9]		RnB interrupt. 0:Disable, 1:Enable
	// RnB_TrandMode[8]		RnB transition detection config. 0:Low to High, 1:High to Low
	// SpareECCLock	[6]		0:Unlock, 1:Lock
	// MainECCLock	[5]		0:Unlock, 1:Lock
	// InitECC(W)	[4]		1:Init ECC decoder/encoder.
	// Reg_nCE		[1]		0:nFCE=0, 1:nFCE=1.
	// NANDC Enable	[0]		operating mode. 0:Disable, 1:Enable.

//	rNFSTAT = 0;
    
//    Nand_Reset();
}