📄 mmu.txt
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; generated by ARM C Compiler, ADS1.2 [Build 805]
; commandline [-errors .\err\mmu.err -O0 -asm -g+ -cpu ARM920T -fs "-IC:\Program Files\ARM\ADSv1_2\INCLUDE"]
CODE32
AREA ||.text||, CODE, READONLY
MMU_SetMTT PROC
;;;100 void MMU_SetMTT(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
;;;101 {
000000 e92d4070 STMFD sp!,{r4-r6,lr}
;;;102 volatile U32 *pTT;
;;;103 volatile int i,nSec;
;;;104 pTT=(U32 *)_MMUTT_STARTADDRESS+(vaddrStart>>20);
000004 e1a05a40 MOV r5,r0,ASR #20
000008 e59f627c LDR r6,|L1.652|
00000c e086e105 ADD lr,r6,r5,LSL #2
;;;105 nSec=(vaddrEnd>>20)-(vaddrStart>>20);
000010 e1a05a41 MOV r5,r1,ASR #20
000014 e0455a40 SUB r5,r5,r0,ASR #20
000018 e1a04005 MOV r4,r5
;;;106 for(i=0;i<=nSec;i++)*pTT++=attr |(((paddrStart>>20)+i)<<20);
00001c e3a05000 MOV r5,#0
000020 e1a0c005 MOV r12,r5
|L1.36|
000024 e15c0004 CMP r12,r4
000028 ca000008 BGT |L1.80|
00002c ea000002 B |L1.60|
|L1.48|
000030 e28c5001 ADD r5,r12,#1
000034 e1a0c005 MOV r12,r5
000038 eafffff9 B |L1.36|
|L1.60|
00003c e08c5a42 ADD r5,r12,r2,ASR #20
000040 e1835a05 ORR r5,r3,r5,LSL #20
000044 e58e5000 STR r5,[lr,#0]
000048 e28ee004 ADD lr,lr,#4
00004c eafffff7 B |L1.48|
;;;107 }
|L1.80|
000050 e8bd8070 LDMFD sp!,{r4-r6,pc}
ENDP
MMU_Init PROC
;;;20 void MMU_Init(void)
;;;21 {
000054 e92d4038 STMFD sp!,{r3-r5,lr}
;;;22 int i,j;
;;;23 //========================== IMPORTANT NOTE =========================
;;;24 //The current stack and code area can't be re-mapped in this routine.
;;;25 //If you want memory map mapped freely, your own sophiscated MMU
;;;26 //initialization code is needed.
;;;27 //===================================================================
;;;28
;;;29 //If write-back is used,the DCache should be cleared. Dcache must be enabled.
;;;30 for(i=0;i<64;i++)
000058 e3a05000 MOV r5,#0
|L1.92|
00005c e3550040 CMP r5,#0x40
000060 aa00000d BGE |L1.156|
000064 ea000001 B |L1.112|
|L1.104|
000068 e2855001 ADD r5,r5,#1
00006c eafffffa B |L1.92|
;;;31 for(j=0;j<8;j++)
|L1.112|
000070 e3a04000 MOV r4,#0
|L1.116|
000074 e3540008 CMP r4,#8
000078 aa000006 BGE |L1.152|
00007c ea000001 B |L1.136|
|L1.128|
000080 e2844001 ADD r4,r4,#1
000084 eafffffa B |L1.116|
;;;32 MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
|L1.136|
000088 e1a01d05 MOV r1,r5,LSL #26
00008c e1810284 ORR r0,r1,r4,LSL #5
000090 ebfffffe BL MMU_CleanInvalidateDCacheIndex
000094 eafffff9 B |L1.128|
|L1.152|
000098 eafffff2 B |L1.104|
;;;33
;;;34 MMU_DisableDCache();
|L1.156|
00009c ebfffffe BL MMU_DisableDCache
;;;35 MMU_DisableICache();
0000a0 ebfffffe BL MMU_DisableICache
;;;36
;;;37 MMU_InvalidateICache();
0000a4 ebfffffe BL MMU_InvalidateICache
;;;38
;;;39 #if 0
;;;40 //To complete MMU_Init() fast, Icache may be turned on here.
;;;41 MMU_EnableICache();
;;;42 #endif
;;;43
;;;44 MMU_DisableMMU();
0000a8 ebfffffe BL MMU_DisableMMU
;;;45 MMU_InvalidateTLB();
0000ac ebfffffe BL MMU_InvalidateTLB
;;;46
;;;47 //MMU_SetMTT(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
;;;48 MMU_SetMTT(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0
0000b0 e59f31d8 LDR r3,|L1.656|
0000b4 e3a02000 MOV r2,#0
0000b8 e3a0167f MOV r1,#0x7f00000
0000bc e3a00000 MOV r0,#0
0000c0 ebfffffe BL MMU_SetMTT
;;;49 MMU_SetMTT(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1
0000c4 e59f31c4 LDR r3,|L1.656|
0000c8 e3a02680 MOV r2,#0x8000000
0000cc e3a016ff MOV r1,#0xff00000
0000d0 e3a00680 MOV r0,#0x8000000
0000d4 ebfffffe BL MMU_SetMTT
;;;50 MMU_SetMTT(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2
0000d8 e59f31b4 LDR r3,|L1.660|
0000dc e3a02540 MOV r2,#0x10000000
0000e0 e282167f ADD r1,r2,#0x7f00000
0000e4 e3a00540 MOV r0,#0x10000000
0000e8 ebfffffe BL MMU_SetMTT
;;;51 MMU_SetMTT(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3
0000ec e59f31a0 LDR r3,|L1.660|
0000f0 e3a02560 MOV r2,#0x18000000
0000f4 e282167f ADD r1,r2,#0x7f00000
0000f8 e3a00560 MOV r0,#0x18000000
0000fc ebfffffe BL MMU_SetMTT
;;;52 //MMU_SetMTT(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4
;;;53 MMU_SetMTT(0x20000000,0x27f00000,0x20000000,RW_CNB); //bank4 for STRATA Flash
000100 e59f3188 LDR r3,|L1.656|
000104 e3a02580 MOV r2,#0x20000000
000108 e282167f ADD r1,r2,#0x7f00000
00010c e3a00580 MOV r0,#0x20000000
000110 ebfffffe BL MMU_SetMTT
;;;54 MMU_SetMTT(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5
000114 e59f3178 LDR r3,|L1.660|
000118 e3a025a0 MOV r2,#0x28000000
00011c e282167f ADD r1,r2,#0x7f00000
000120 e3a005a0 MOV r0,#0x28000000
000124 ebfffffe BL MMU_SetMTT
;;;55 MMU_SetMTT(0x30000000,0x30f00000,0x30000000,RW_CB); //bank6-1
000128 e59f3168 LDR r3,|L1.664|
00012c e3a025c0 MOV r2,#0x30000000
000130 e28218f0 ADD r1,r2,#0xf00000
000134 e3a005c0 MOV r0,#0x30000000
000138 ebfffffe BL MMU_SetMTT
;;;56 MMU_SetMTT(0x31000000,0x31e00000,0x31000000,RW_NCNB); //bank6-2
00013c e59f3150 LDR r3,|L1.660|
000140 e3a025c4 MOV r2,#0x31000000
000144 e28218e0 ADD r1,r2,#0xe00000
000148 e3a005c4 MOV r0,#0x31000000
00014c ebfffffe BL MMU_SetMTT
;;;57 MMU_SetMTT(0x31f00000,0x31f00000,0x31f00000,RW_CB); //bank6-3
000150 e59f3140 LDR r3,|L1.664|
000154 e59f2140 LDR r2,|L1.668|
000158 e1a01002 MOV r1,r2
00015c e1a00002 MOV r0,r2
000160 ebfffffe BL MMU_SetMTT
;;;58 //MMU_SetMTT(0x31000000,0x33e00000,0x31000000,RW_NCNB); //bank6-2
;;;59 //MMU_SetMTT(0x33f00000,0x33f00000,0x33f00000,RW_CB); //bank6-3
;;;60 MMU_SetMTT(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7
000164 e59f3128 LDR r3,|L1.660|
000168 e3a025e0 MOV r2,#0x38000000
00016c e282167f ADD r1,r2,#0x7f00000
000170 e3a005e0 MOV r0,#0x38000000
000174 ebfffffe BL MMU_SetMTT
;;;61
;;;62 MMU_SetMTT(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR
000178 e59f3114 LDR r3,|L1.660|
00017c e3a02442 MOV r2,#0x40000000
000180 e282167f ADD r1,r2,#0x7f00000
000184 e3a00440 MOV r0,#0x40000000
000188 ebfffffe BL MMU_SetMTT
;;;63 MMU_SetMTT(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
00018c e59f3100 LDR r3,|L1.660|
000190 e3a02448 MOV r2,#0x48000000
000194 e59f1104 LDR r1,|L1.672|
000198 e3a00448 MOV r0,#0x48000000
00019c ebfffffe BL MMU_SetMTT
;;;64 MMU_SetMTT(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR
0001a0 e59f30ec LDR r3,|L1.660|
0001a4 e3a0245b MOV r2,#0x5b000000
0001a8 e3a0145b MOV r1,#0x5b000000
0001ac e3a0045b MOV r0,#0x5b000000
0001b0 ebfffffe BL MMU_SetMTT
;;;65 MMU_SetMTT(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used
0001b4 e59f30e8 LDR r3,|L1.676|
0001b8 e59f20e8 LDR r2,|L1.680|
0001bc e59f10e8 LDR r1,|L1.684|
0001c0 e1a00002 MOV r0,r2
0001c4 ebfffffe BL MMU_SetMTT
;;;66
;;;67 MMU_SetTTBase(_MMUTT_STARTADDRESS);
0001c8 e59f00bc LDR r0,|L1.652|
0001cc ebfffffe BL MMU_SetTTBase
;;;68 MMU_SetDomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
0001d0 e59f00d8 LDR r0,|L1.688|
0001d4 ebfffffe BL MMU_SetDomain
;;;69 //DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked)
;;;70 MMU_SetProcessId(0x0);
0001d8 e3a00000 MOV r0,#0
0001dc ebfffffe BL MMU_SetProcessId
;;;71 MMU_EnableAlignFault();
0001e0 ebfffffe BL MMU_EnableAlignFault
;;;72
;;;73 MMU_EnableMMU();
0001e4 ebfffffe BL MMU_EnableMMU
;;;74 MMU_EnableICache();
0001e8 ebfffffe BL MMU_EnableICache
;;;75 MMU_EnableDCache(); //DCache should be turned on after MMU is turned on.
0001ec ebfffffe BL MMU_EnableDCache
;;;76 }
0001f0 e8bd8038 LDMFD sp!,{r3-r5,pc}
ENDP
ChangeRomCacheStatus PROC
;;;80 void ChangeRomCacheStatus(int attr)
;;;81 {
0001f4 e92d4070 STMFD sp!,{r4-r6,lr}
0001f8 e1a06000 MOV r6,r0
;;;82 int i,j;
;;;83 MMU_DisableDCache();
0001fc ebfffffe BL MMU_DisableDCache
;;;84 MMU_DisableICache();
000200 ebfffffe BL MMU_DisableICache
;;;85 //If write-back is used,the DCache should be cleared.
;;;86 for(i=0;i<64;i++)
000204 e3a05000 MOV r5,#0
|L1.520|
000208 e3550040 CMP r5,#0x40
00020c aa00000d BGE |L1.584|
000210 ea000001 B |L1.540|
|L1.532|
000214 e2855001 ADD r5,r5,#1
000218 eafffffa B |L1.520|
;;;87 for(j=0;j<8;j++)
|L1.540|
00021c e3a04000 MOV r4,#0
|L1.544|
000220 e3540008 CMP r4,#8
000224 aa000006 BGE |L1.580|
000228 ea000001 B |L1.564|
|L1.556|
00022c e2844001 ADD r4,r4,#1
000230 eafffffa B |L1.544|
;;;88 MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
|L1.564|
000234 e1a01d05 MOV r1,r5,LSL #26
000238 e1810284 ORR r0,r1,r4,LSL #5
00023c ebfffffe BL MMU_CleanInvalidateDCacheIndex
000240 eafffff9 B |L1.556|
|L1.580|
000244 eafffff2 B |L1.532|
;;;89 MMU_InvalidateICache();
|L1.584|
000248 ebfffffe BL MMU_InvalidateICache
;;;90 MMU_DisableMMU();
00024c ebfffffe BL MMU_DisableMMU
;;;91 MMU_InvalidateTLB();
000250 ebfffffe BL MMU_InvalidateTLB
;;;92 MMU_SetMTT(0x00000000,0x07f00000,0x00000000,attr); //bank0
000254 e1a03006 MOV r3,r6
000258 e3a02000 MOV r2,#0
00025c e3a0167f MOV r1,#0x7f00000
000260 e3a00000 MOV r0,#0
000264 ebfffffe BL MMU_SetMTT
;;;93 MMU_SetMTT(0x08000000,0x0ff00000,0x08000000,attr); //bank1
000268 e1a03006 MOV r3,r6
00026c e3a02680 MOV r2,#0x8000000
000270 e3a016ff MOV r1,#0xff00000
000274 e3a00680 MOV r0,#0x8000000
000278 ebfffffe BL MMU_SetMTT
;;;94 MMU_EnableMMU();
00027c ebfffffe BL MMU_EnableMMU
;;;95 MMU_EnableICache();
000280 ebfffffe BL MMU_EnableICache
;;;96 MMU_EnableDCache();
000284 ebfffffe BL MMU_EnableDCache
;;;97 }
000288 e8bd8070 LDMFD sp!,{r4-r6,pc}
|L1.652|
00028c 31ff8000 DCD 0x31ff8000
|L1.656|
000290 00000c1a DCD 0x00000c1a
|L1.660|
000294 00000c12 DCD 0x00000c12
|L1.664|
000298 00000c1e DCD 0x00000c1e
|L1.668|
00029c 31f00000 DCD 0x31f00000
|L1.672|
0002a0 5af00000 DCD 0x5af00000
|L1.676|
0002a4 00000c32 DCD 0x00000c32
|L1.680|
0002a8 5b100000 DCD 0x5b100000
|L1.684|
0002ac fff00000 DCD 0xfff00000
|L1.688|
0002b0 55555551 DCD 0x55555551
ENDP
END
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