📄 strata32.txt
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;;;153 return 0;
000204 e3a00000 MOV r0,#0
;;;154 }
;;;155 }
;;;156 return 1;
;;;157 }
|L1.520|
000208 e8bd80f8 LDMFD sp!,{r3-r7,pc}
|L1.524|
00020c eafffff3 B |L1.480| ;155
|L1.528|
000210 e3a00001 MOV r0,#1 ;156
000214 eafffffb B |L1.520| ;156
|L1.536|
000218 203a2045 DCB "E : " ;156
00021c 3d207825 DCB "%x =" ;156
000220 0a782520 DCB " %x\n" ;156
000224 00000000 DCB "\0\0\0\0" ;156
ENDP
Strata_ProgFlash PROC
;;;160 int Strata_ProgFlash(U32 realAddr,U32 data)
;;;161 {
000228 e92d40f0 STMFD sp!,{r4-r7,lr}
00022c e1a02000 MOV r2,r0
;;;162 volatile U32 *ptargetAddr;
;;;163 unsigned long ReadStatus;
;;;164 unsigned long bSR4; // Erase and Clear Lock-bits Status, lower 16bit, 8MB Intel Strate Flash ROM
;;;165 unsigned long bSR4_2; // Erase and Clear Lock-bits Status, higher 16bit, 8MB Intel Strate Flash ROM
;;;166 unsigned long bSR7; // Write State Machine Status, lower 16bit, 8MB Intel Strate Flash ROM
;;;167 unsigned long bSR7_2; // Write State Machine Status, higher 16bit, 8MB Intel Strate Flash ROM
;;;168
;;;169 ptargetAddr = (volatile U32 *)realAddr;
000230 e1a04002 MOV r4,r2
;;;170 //_RESET();
;;;171
;;;172 _WR(realAddr, 0x00400040); // realAddr is any valid adress within the device
000234 e59f0104 LDR r0,|L1.832|
000238 e5820000 STR r0,[r2,#0]
;;;173 // Word/Byte Program(or 0x00100010 can be used)
;;;174 *ptargetAddr=data; // 32 bit data
00023c e1a02004 MOV r2,r4
000240 e5841000 STR r1,[r4,#0]
;;;175
;;;176 //_RESET();
;;;177 _WR(realAddr, 0x00700070); // Read Status Register
000244 e51f00ac LDR r0,|L1.416|
000248 e5820000 STR r0,[r2,#0]
;;;178 ReadStatus=_RD(realAddr); // realAddr is any valid address within the device
00024c e5920000 LDR r0,[r2,#0]
000250 e1a03000 MOV r3,r0
;;;179 bSR7=ReadStatus & (1<<7);
000254 e203c080 AND r12,r3,#0x80
;;;180 bSR7_2=ReadStatus & (1<<(7+16));
000258 e203e880 AND lr,r3,#0x800000
;;;181 while(!bSR7 || !bSR7_2)
00025c e1a00000 NOP
|L1.608|
000260 e35c0000 CMP r12,#0
000264 0a000001 BEQ |L1.624|
000268 e35e0000 CMP lr,#0
00026c 1a000006 BNE |L1.652|
;;;182 {
;;;183 // _RESET();
;;;184 _WR(realAddr, 0x00700070); // Read Status Register
|L1.624|
000270 e51f00d8 LDR r0,|L1.416|
000274 e5820000 STR r0,[r2,#0]
;;;185 ReadStatus=_RD(realAddr);
000278 e5920000 LDR r0,[r2,#0]
00027c e1a03000 MOV r3,r0
;;;186 bSR7=ReadStatus & (1<<7);
000280 e203c080 AND r12,r3,#0x80
;;;187 bSR7_2=ReadStatus & (1<<(7+16));
000284 e203e880 AND lr,r3,#0x800000
;;;188 }
000288 eafffff4 B |L1.608|
;;;189
;;;190 _WR(realAddr, 0x00700070);
|L1.652|
00028c e51f00f4 LDR r0,|L1.416|
000290 e5820000 STR r0,[r2,#0]
;;;191 ReadStatus=_RD(realAddr); // Real Status Register
000294 e5920000 LDR r0,[r2,#0]
000298 e1a03000 MOV r3,r0
;;;192 bSR4=ReadStatus & (1<<4);
00029c e2035010 AND r5,r3,#0x10
;;;193 bSR4_2=ReadStatus & (1<<(4+16));
0002a0 e2036940 AND r6,r3,#0x100000
;;;194
;;;195 if (bSR4==0 && bSR4_2==0)
0002a4 e1950006 ORRS r0,r5,r6
0002a8 0a000004 BEQ |L1.704|
;;;196 {
;;;197 //Uart_Printf("Successful Program!!\n");
;;;198 ;
;;;199 }
;;;200 else
;;;201 {
;;;202 //Uart_Printf("Error Program!!\n");
;;;203 _WR(realAddr, 0x00500050); // Clear Status Register
0002ac e51f00f8 LDR r0,|L1.444|
0002b0 e5820000 STR r0,[r2,#0]
;;;204 error_program=1; // But not major, is it casual ?
0002b4 e3a00001 MOV r0,#1
0002b8 e59f7084 LDR r7,|L1.836|
0002bc e5870000 STR r0,[r7,#0] ; error_program
;;;205 }
;;;206
;;;207 _RESET();
|L1.704|
0002c0 e51f0144 LDR r0,|L1.388|
0002c4 e51f7144 LDR r7,|L1.392|
0002c8 e5977000 LDR r7,[r7,#0] ; targetAddress
0002cc e5870000 STR r0,[r7,#0]
;;;208 return 0;
0002d0 e3a00000 MOV r0,#0
;;;209 }
0002d4 e8bd80f0 LDMFD sp!,{r4-r7,pc}
ENDP
InputAddresses PROC
;;;390 static void InputAddresses(void)
;;;391 {
0002d8 e92d4008 STMFD sp!,{r3,lr}
;;;392 Uart_Printf("\n[ 28F128J3A Writing Program ]\n");
0002dc e28f0064 ADR r0,|L1.840|
0002e0 ebfffffe BL Uart_Printf
;;;393
;;;394 Uart_Printf("\nSource size [0x?] : 0h~%xh\n",downloadProgramSize);
0002e4 e59f007c LDR r0,|L1.872|
0002e8 e5901000 LDR r1,[r0,#0] ; downloadProgramSize
0002ec e28f0078 ADR r0,|L1.876|
0002f0 ebfffffe BL Uart_Printf
;;;395 Uart_Printf("\nAvailable Target Offset Address [0x?] : \n");
0002f4 e28f0090 ADR r0,|L1.908|
0002f8 ebfffffe BL Uart_Printf
;;;396 Uart_Printf("0h,20000h,40000h, ..., 1ce0000h\n");
0002fc e28f00b4 ADR r0,|L1.952|
000300 ebfffffe BL Uart_Printf
;;;397 Uart_Printf("Input target address offset [0x?] : ");
000304 e28f00d0 ADR r0,|L1.988|
000308 ebfffffe BL Uart_Printf
;;;398 targetOffset=Uart_GetIntNum();
00030c ebfffffe BL Uart_GetIntNum
000310 e59f10ec LDR r1,|L1.1028|
000314 e5810000 STR r0,[r1,#0] ; targetOffset
;;;399 if(targetSize==0)
000318 e59f00e8 LDR r0,|L1.1032|
00031c e5900000 LDR r0,[r0,#0] ; targetSize
000320 e3500000 CMP r0,#0
000324 1a000004 BNE |L1.828|
;;;400 {
;;;401 Uart_Printf("Input target size [0x?] : ");
000328 e28f00dc ADR r0,|L1.1036|
00032c ebfffffe BL Uart_Printf
;;;402 targetSize=Uart_GetIntNum();
000330 ebfffffe BL Uart_GetIntNum
000334 e59f10cc LDR r1,|L1.1032|
000338 e5810000 STR r0,[r1,#0] ; targetSize
;;;403 }
;;;404 }
|L1.828|
00033c e8bd8008 LDMFD sp!,{r3,pc}
|L1.832|
000340 00400040 DCD 0x00400040
|L1.836|
000344 00000004 DCD ||.bss$2|| + 4
|L1.840|
000348 32205b0a DCB "\n[ 2"
00034c 32314638 DCB "8F12"
000350 41334a38 DCB "8J3A"
000354 69725720 DCB " Wri"
000358 676e6974 DCB "ting"
00035c 6f725020 DCB " Pro"
000360 6d617267 DCB "gram"
000364 000a5d20 DCB " ]\n\0"
|L1.872|
000368 00000000 DCD downloadProgramSize
|L1.876|
00036c 756f530a DCB "\nSou"
000370 20656372 DCB "rce "
000374 657a6973 DCB "size"
000378 78305b20 DCB " [0x"
00037c 3a205d3f DCB "?] :"
000380 7e683020 DCB " 0h~"
000384 0a687825 DCB "%xh\n"
000388 00000000 DCB "\0\0\0\0"
|L1.908|
00038c 6176410a DCB "\nAva"
000390 62616c69 DCB "ilab"
000394 5420656c DCB "le T"
000398 65677261 DCB "arge"
00039c 664f2074 DCB "t Of"
0003a0 74657366 DCB "fset"
0003a4 64644120 DCB " Add"
0003a8 73736572 DCB "ress"
0003ac 78305b20 DCB " [0x"
0003b0 3a205d3f DCB "?] :"
0003b4 00000a20 DCB " \n\0\0"
|L1.952|
0003b8 322c6830 DCB "0h,2"
0003bc 30303030 DCB "0000"
0003c0 30342c68 DCB "h,40"
0003c4 68303030 DCB "000h"
0003c8 2e2e202c DCB ", .."
0003cc 31202c2e DCB "., 1"
0003d0 30306563 DCB "ce00"
0003d4 0a683030 DCB "00h\n"
0003d8 00000000 DCB "\0\0\0\0"
|L1.988|
0003dc 75706e49 DCB "Inpu"
0003e0 61742074 DCB "t ta"
0003e4 74656772 DCB "rget"
0003e8 64646120 DCB " add"
0003ec 73736572 DCB "ress"
0003f0 66666f20 DCB " off"
0003f4 20746573 DCB "set "
0003f8 3f78305b DCB "[0x?"
0003fc 203a205d DCB "] : "
000400 00000000 DCB "\0\0\0\0"
|L1.1028|
000404 0000000c DCD ||.bss$2|| + 12
|L1.1032|
000408 00000014 DCD ||.bss$2|| + 20
|L1.1036|
00040c 75706e49 DCB "Inpu"
000410 61742074 DCB "t ta"
000414 74656772 DCB "rget"
000418 7a697320 DCB " siz"
00041c 305b2065 DCB "e [0"
000420 205d3f78 DCB "x?] "
000424 0000203a DCB ": \0\0"
ENDP
Program28F128J3A PROC
;;;216 void Program28F128J3A(void)
;;;217 {
000428 e92d4038 STMFD sp!,{r3-r5,lr}
;;;218 // FlashROM write program must reside at RAM region NOT ROM region
;;;219 // In reading and writing all interrupts are disabled because the flash ROM
;;;220 // strongly dislike to be disturbed by other stuff.
;;;221 // And the region of flash ROM must be I/O region which means NO cacheable
;;;222 // and NO bufferable in MMU. Check it out !!!
;;;223 // 2001.6.18. Mon. It's local rain. I'll hope it eliminates the drought in Korea. by chc
;;;224
;;;225 unsigned long interrupt_reservoir;
;;;226 int i;
;;;227
;;;228 Uart_Printf("\n[ 28F128J3A Flash Writing Program ]\n\n");
00042c e28f0f42 ADR r0,|L1.1340|
000430 ebfffffe BL Uart_Printf
;;;229 Uart_Printf(" *** Very Important Notes ***\n");
000434 e28f0f4a ADR r0,|L1.1380|
000438 ebfffffe BL Uart_Printf
;;;230 Uart_Printf("1. 28F128J3A must be located at 0x08000000.\n"
00043c e59f0144 LDR r0,|L1.1416|
000440 ebfffffe BL Uart_Printf
;;;231 " J1:1-2, J2:2-3, J3:2-3, J4:1-2 \n");
;;;232 Uart_Printf("2. After programming, 28F128J3A may be located at 0x0.\n"
000444 e59f0140 LDR r0,|L1.1420|
000448 ebfffffe BL Uart_Printf
;;;233 " J1:2-3, J2:1-2, J3:1-2, J4:2-3 \n");
;;;234
;;;235 rINTMSK = BIT_ALLMSK;
00044c e3e00000 MVN r0,#0
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