📄 strata32.txt
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; generated by ARM C Compiler, ADS1.2 [Build 805]
; commandline [-errors .\err\strata32.err -O0 -asm -g+ -cpu ARM920T -fs "-IC:\Program Files\ARM\ADSv1_2\INCLUDE"]
CODE32
AREA ||.text||, CODE, READONLY
Strata_CheckID PROC
;;;55 int Strata_CheckID(int targetAddr)
;;;56 {
|L1.0|
000000 e1a01000 MOV r1,r0
;;;57 _RESET();
000004 e59f0178 LDR r0,|L1.388|
000008 e59f2178 LDR r2,|L1.392|
00000c e5922000 LDR r2,[r2,#0] ; targetAddress
000010 e5820000 STR r0,[r2,#0]
;;;58 _WR(targetAddr, 0x00900090);
000014 e59f0170 LDR r0,|L1.396|
000018 e5810000 STR r0,[r1,#0]
;;;59 return _RD(targetAddr); // Read Identifier Code, including lower, higher 16-bit, 8MB, Intel Strate Flash ROM
00001c e5910000 LDR r0,[r1,#0]
;;;60 // targetAddress must be the beginning location of a Block Address
;;;61 }
000020 e1a0f00e MOV pc,lr
ENDP
Strata_CheckDevice PROC
;;;64 int Strata_CheckDevice(int targetAddr)
;;;65 {
000024 e1a01000 MOV r1,r0
;;;66 _RESET();
000028 e59f0154 LDR r0,|L1.388|
00002c e59f2154 LDR r2,|L1.392|
000030 e5922000 LDR r2,[r2,#0] ; targetAddress
000034 e5820000 STR r0,[r2,#0]
;;;67 _WR(targetAddr, 0x00900090);
000038 e59f014c LDR r0,|L1.396|
00003c e5810000 STR r0,[r1,#0]
;;;68 return _RD(targetAddr+0x4); // Read Device Code, including lower, higher 16-bit, 8MB, Intel Strate Flash ROM
000040 e5910004 LDR r0,[r1,#4]
;;;69 // targetAddress must be the beginning location of a Block Address
;;;70 }
000044 e1a0f00e MOV pc,lr
ENDP
Strata_CheckBlockLock PROC
;;;73 int Strata_CheckBlockLock(int targetAddr)
;;;74 {
000048 e1a01000 MOV r1,r0
;;;75 _RESET();
00004c e59f0130 LDR r0,|L1.388|
000050 e59f2130 LDR r2,|L1.392|
000054 e5922000 LDR r2,[r2,#0] ; targetAddress
000058 e5820000 STR r0,[r2,#0]
;;;76 _WR(targetAddr, 0x00900090);
00005c e59f0128 LDR r0,|L1.396|
000060 e5810000 STR r0,[r1,#0]
;;;77 return _RD(targetAddr+0x8); // Read Block Lock configuration,
000064 e5910008 LDR r0,[r1,#8]
;;;78 // targetAddress must be the beginning location of a Block Address
;;;79 }
000068 e1a0f00e MOV pc,lr
ENDP
Strata_Unlock PROC
;;;81 void Strata_Unlock(int targetAddr)
;;;82 {
00006c e59f1110 LDR r1,|L1.388|
;;;83 _RESET();
000070 e59f2110 LDR r2,|L1.392|
000074 e5922000 LDR r2,[r2,#0] ; targetAddress
000078 e5821000 STR r1,[r2,#0]
;;;84 _WR(targetAddr, 0x00600060);
00007c e59f110c LDR r1,|L1.400|
000080 e5801000 STR r1,[r0,#0]
;;;85 _WR(targetAddr, 0x00D000D0);
000084 e59f1108 LDR r1,|L1.404|
000088 e5801000 STR r1,[r0,#0]
;;;86 }
00008c e1a0f00e MOV pc,lr
ENDP
Strata_SetBlockLock PROC
;;;88 void Strata_SetBlockLock(int targetAddr)
;;;89 {
000090 e59f10ec LDR r1,|L1.388|
;;;90 _RESET();
000094 e59f20ec LDR r2,|L1.392|
000098 e5922000 LDR r2,[r2,#0] ; targetAddress
00009c e5821000 STR r1,[r2,#0]
;;;91 _WR(targetAddr, 0x00600060);
0000a0 e59f10e8 LDR r1,|L1.400|
0000a4 e5801000 STR r1,[r0,#0]
;;;92 _WR(targetAddr, 0x00010001);
0000a8 e59f10e8 LDR r1,|L1.408|
0000ac e5801000 STR r1,[r0,#0]
;;;93 }
0000b0 e1a0f00e MOV pc,lr
ENDP
Strata_EraseSector PROC
;;;96 void Strata_EraseSector(int targetAddress)
;;;97 {
0000b4 e92d43f8 STMFD sp!,{r3-r9,lr}
0000b8 e1a04000 MOV r4,r0
;;;98 unsigned long ReadStatus;
;;;99 unsigned long bSR5; // Erase and Clear Lock-bits Status, lower 16bit, 8MB Intel Strate Flash ROM
;;;100 unsigned long bSR5_2; // Erase and Clear Lock-bits Status, higher 16bit, 8MB Intel Strate Flash ROM
;;;101 unsigned long bSR7; // Write State Machine Status, lower 16bit, 8MB Intel Strate Flash ROM
;;;102 unsigned long bSR7_2; // Write State Machine Status, higher 16bit, 8MB Intel Strate Flash ROM
;;;103 //_RESET();
;;;104 // _WR(targetAddress, 0x00200020);
;;;105 // _WR(targetAddress, 0x00d000d0);
;;;106 _WR(targetAddress, 0x00200020); // Block Erase, First Bus Cycle, targetAddress is the address withint the block
0000bc e59f00d8 LDR r0,|L1.412|
0000c0 e5840000 STR r0,[r4,#0]
;;;107 _WR(targetAddress, 0x00d000d0); // Block Erase, Second Bus Cycle, targetAddress is the address withint the block
0000c4 e59f00c8 LDR r0,|L1.404|
0000c8 e5840000 STR r0,[r4,#0]
;;;108
;;;109 //_RESET();
;;;110 _WR(targetAddress, 0x00700070); // Read Status Register, First Bus Cycle, targetAddress is any valid address within the device
0000cc e59f00cc LDR r0,|L1.416|
0000d0 e5840000 STR r0,[r4,#0]
;;;111 ReadStatus=_RD(targetAddress); // Read Status Register, Second Bus Cycle, targetAddress is any valid address within the device
0000d4 e5940000 LDR r0,[r4,#0]
0000d8 e1a05000 MOV r5,r0
;;;112 bSR7=ReadStatus & (1<<7); // lower 16-bit 8MB Strata
0000dc e2056080 AND r6,r5,#0x80
;;;113 bSR7_2=ReadStatus & (1<<(7+16));// higher 16-bit 8MB Strata
0000e0 e2057880 AND r7,r5,#0x800000
;;;114 while(!bSR7 | !bSR7_2)
0000e4 e1a00000 NOP
|L1.232|
0000e8 e3560000 CMP r6,#0
0000ec 1a000001 BNE |L1.248|
0000f0 e3a00001 MOV r0,#1
0000f4 ea000000 B |L1.252|
|L1.248|
0000f8 e3a00000 MOV r0,#0
|L1.252|
0000fc e3570000 CMP r7,#0
000100 1a000001 BNE |L1.268|
000104 e3a01001 MOV r1,#1
000108 ea000000 B |L1.272|
|L1.268|
00010c e3a01000 MOV r1,#0
|L1.272|
000110 e1900001 ORRS r0,r0,r1
000114 0a000006 BEQ |L1.308|
;;;115 {
;;;116 _WR(targetAddress, 0x00700070);
000118 e59f0080 LDR r0,|L1.416|
00011c e5840000 STR r0,[r4,#0]
;;;117 ReadStatus=_RD(targetAddress);
000120 e5940000 LDR r0,[r4,#0]
000124 e1a05000 MOV r5,r0
;;;118 bSR7=ReadStatus & (1<<7);
000128 e2056080 AND r6,r5,#0x80
;;;119 bSR7_2=ReadStatus & (1<<(7+16));
00012c e2057880 AND r7,r5,#0x800000
;;;120 // Uart_Printf("wait !!\n");
;;;121 }
000130 eaffffec B |L1.232|
;;;122
;;;123 _WR(targetAddress, 0x00700070); // When the block erase is complete, status register bit SR.5 should be checked.
|L1.308|
000134 e59f0064 LDR r0,|L1.416|
000138 e5840000 STR r0,[r4,#0]
;;;124 // If a block erase error is detected, the status register should be cleared before
;;;125 // system software attempts correct actions.
;;;126 ReadStatus=_RD(targetAddress);
00013c e5940000 LDR r0,[r4,#0]
000140 e1a05000 MOV r5,r0
;;;127 bSR5=ReadStatus & (1<<5); // lower 16-bit 8MB Strata
000144 e2058020 AND r8,r5,#0x20
;;;128 bSR5_2=ReadStatus & (1<<(5+16)); // higher 16-bit 8MB Strata
000148 e2059980 AND r9,r5,#0x200000
;;;129 if (bSR5==0 && bSR5_2==0)
00014c e1980009 ORRS r0,r8,r9
000150 1a000003 BNE |L1.356|
;;;130 {
;;;131 Uart_Printf("Block_%x Erase O.K. \n",targetAddress);
000154 e1a01004 MOV r1,r4
000158 e28f0044 ADR r0,|L1.420|
00015c ebfffffe BL Uart_Printf
000160 ea000004 B |L1.376|
;;;132 }
;;;133 else
;;;134 {
;;;135 //Uart_Printf("Error in Block Erasure!!\n");
;;;136 _WR(targetAddress, 0x00500050); // Clear Status Register
|L1.356|
000164 e59f0050 LDR r0,|L1.444|
000168 e5840000 STR r0,[r4,#0]
;;;137 error_erase=1; // But not major, is it casual ?
00016c e3a00001 MOV r0,#1
000170 e59f1048 LDR r1,|L1.448|
000174 e5810000 STR r0,[r1,#0] ; error_erase
;;;138 }
;;;139
;;;140 _RESET(); // write 0xffh(_RESET()) after the last opoeration to reset the device to read array mode.
|L1.376|
000178 e59f0004 LDR r0,|L1.388|
00017c e5840000 STR r0,[r4,#0]
;;;141 }
000180 e8bd83f8 LDMFD sp!,{r3-r9,pc}
|L1.388|
000184 00ff00ff DCD 0x00ff00ff
|L1.392|
000188 00000010 DCD ||.bss$2|| + 16
|L1.396|
00018c 00900090 DCD 0x00900090
|L1.400|
000190 00600060 DCD 0x00600060
|L1.404|
000194 00d000d0 DCD 0x00d000d0
|L1.408|
000198 00010001 DCD 0x00010001
|L1.412|
00019c 00200020 DCD 0x00200020
|L1.416|
0001a0 00700070 DCD 0x00700070
|L1.420|
0001a4 636f6c42 DCB "Bloc"
0001a8 78255f6b DCB "k_%x"
0001ac 61724520 DCB " Era"
0001b0 4f206573 DCB "se O"
0001b4 202e4b2e DCB ".K. "
0001b8 0000000a DCB "\n\0\0\0"
|L1.444|
0001bc 00500050 DCD 0x00500050
|L1.448|
0001c0 00000000 DCD ||.bss$2||
ENDP
Strata_BlankCheck PROC
;;;144 int Strata_BlankCheck(int targetAddr,int targetSize)
;;;145 {
0001c4 e92d40f8 STMFD sp!,{r3-r7,lr}
0001c8 e1a06000 MOV r6,r0
0001cc e1a07001 MOV r7,r1
;;;146 int i,j;
;;;147 for (i=0; i<targetSize; i+=4)
0001d0 e3a04000 MOV r4,#0
|L1.468|
0001d4 e1540007 CMP r4,r7
0001d8 aa00000c BGE |L1.528|
0001dc ea000001 B |L1.488|
|L1.480|
0001e0 e2844004 ADD r4,r4,#4
0001e4 eafffffa B |L1.468|
;;;148 {
;;;149 j=*((volatile U32 *)(i+targetAddr));
|L1.488|
0001e8 e7945006 LDR r5,[r4,r6]
;;;150 if (j!=0xffffffff) // In erasure it changes all block dta to 0xff
0001ec e3750001 CMN r5,#1
0001f0 0a000005 BEQ |L1.524|
;;;151 {
;;;152 Uart_Printf("E : %x = %x\n", (i+targetAddr), j);
0001f4 e0841006 ADD r1,r4,r6
0001f8 e1a02005 MOV r2,r5
0001fc e28f0014 ADR r0,|L1.536|
000200 ebfffffe BL Uart_Printf
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