📄 xmain.txt
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; generated by ARM C Compiler, ADS1.2 [Build 805]
; commandline [-errors .\err\xmain.err -O0 -asm -g+ -cpu ARM920T -fs "-IC:\Program Files\ARM\ADSv1_2\INCLUDE"]
CODE32
AREA ||.text||, CODE, READONLY
Clk1_Enable PROC
;;;325 void Clk1_Enable(int clock_sel)
;;;326 { // 0:MPLLout, 1:UPLL, 2:RTC, 3:HCLK, 4:PCLK, 5:DCLK1
000000 e3a01456 MOV r1,#0x56000000
;;;327 rMISCCR = rMISCCR&~(7<<8) | (clock_sel<<8);
000004 e5911080 LDR r1,[r1,#0x80]
000008 e3c11e70 BIC r1,r1,#0x700
00000c e1811400 ORR r1,r1,r0,LSL #8
000010 e3a02456 MOV r2,#0x56000000
000014 e5821080 STR r1,[r2,#0x80]
;;;328 rGPHCON = rGPHCON&~(3<<20) | (2<<20);
000018 e3a01456 MOV r1,#0x56000000
00001c e5911070 LDR r1,[r1,#0x70]
000020 e3c119c0 BIC r1,r1,#0x300000
000024 e3811980 ORR r1,r1,#0x200000
000028 e3a02456 MOV r2,#0x56000000
00002c e5821070 STR r1,[r2,#0x70]
;;;329 }
000030 e1a0f00e MOV pc,lr
ENDP
Clk0_Enable PROC
;;;320 void Clk0_Enable(int clock_sel)
;;;321 { // 0:MPLLin, 1:UPLL, 2:FCLK, 3:HCLK, 4:PCLK, 5:DCLK0
000034 e3a01456 MOV r1,#0x56000000
;;;322 rMISCCR = rMISCCR&~(7<<4) | (clock_sel<<4);
000038 e5911080 LDR r1,[r1,#0x80]
00003c e3c11070 BIC r1,r1,#0x70
000040 e1811200 ORR r1,r1,r0,LSL #4
000044 e3a02456 MOV r2,#0x56000000
000048 e5821080 STR r1,[r2,#0x80]
;;;323 rGPHCON = rGPHCON&~(3<<18) | (2<<18);
00004c e3a01456 MOV r1,#0x56000000
000050 e5911070 LDR r1,[r1,#0x70]
000054 e3c11ac0 BIC r1,r1,#0xc0000
000058 e3811a80 ORR r1,r1,#0x80000
00005c e3a02456 MOV r2,#0x56000000
000060 e5821070 STR r1,[r2,#0x70]
;;;324 }
000064 e1a0f00e MOV pc,lr
ENDP
HaltDabort PROC
;;;314 void HaltDabort(void)
;;;315 {
000068 e92d4008 STMFD sp!,{r3,lr}
;;;316 Uart_Printf("Dabort exception.\n");
00006c e28f0008 ADR r0,|L1.124|
000070 ebfffffe BL Uart_Printf
;;;317 while(1);
000074 e1a00000 NOP
|L1.120|
000078 eafffffe B |L1.120|
|L1.124|
00007c 6f626144 DCB "Dabo"
000080 65207472 DCB "rt e"
000084 70656378 DCB "xcep"
000088 6e6f6974 DCB "tion"
00008c 00000a2e DCB ".\n\0\0"
;;;318 }
ENDP
HaltPabort PROC
;;;307 void HaltPabort(void)
;;;308 {
000090 e92d4008 STMFD sp!,{r3,lr}
;;;309 Uart_Printf("Pabort exception.\n");
000094 e28f0008 ADR r0,|L1.164|
000098 ebfffffe BL Uart_Printf
;;;310 while(1);
00009c e1a00000 NOP
|L1.160|
0000a0 eafffffe B |L1.160|
|L1.164|
0000a4 6f626150 DCB "Pabo"
0000a8 65207472 DCB "rt e"
0000ac 70656378 DCB "xcep"
0000b0 6e6f6974 DCB "tion"
0000b4 00000a2e DCB ".\n\0\0"
;;;311 }
ENDP
HaltSwi PROC
;;;298 void HaltSwi(void)
;;;299 {
0000b8 e92d4008 STMFD sp!,{r3,lr}
;;;300 #if !SEMIHOSTING
;;;301 Uart_Printf("SWI exception!!!\n");
0000bc e28f0008 ADR r0,|L1.204|
0000c0 ebfffffe BL Uart_Printf
;;;302 while(1);
0000c4 e1a00000 NOP
|L1.200|
0000c8 eafffffe B |L1.200|
|L1.204|
0000cc 20495753 DCB "SWI "
0000d0 65637865 DCB "exce"
0000d4 6f697470 DCB "ptio"
0000d8 2121216e DCB "n!!!"
0000dc 0000000a DCB "\n\0\0\0"
;;;303 #endif
;;;304 }
ENDP
HaltUndef PROC
;;;291 void HaltUndef(void)
;;;292 {
0000e0 e92d4008 STMFD sp!,{r3,lr}
;;;293 Uart_Printf("Undefined instruction exception.\n");
0000e4 e28f0008 ADR r0,|L1.244|
0000e8 ebfffffe BL Uart_Printf
;;;294 while(1);
0000ec e1a00000 NOP
|L1.240|
0000f0 eafffffe B |L1.240|
|L1.244|
0000f4 65646e55 DCB "Unde"
0000f8 656e6966 DCB "fine"
0000fc 6e692064 DCB "d in"
000100 75727473 DCB "stru"
000104 6f697463 DCB "ctio"
000108 7865206e DCB "n ex"
00010c 74706563 DCB "cept"
000110 2e6e6f69 DCB "ion."
000114 0000000a DCB "\n\0\0\0"
;;;295 }
ENDP
Isr_Init PROC
;;;272 void Isr_Init(void)
;;;273 {
000118 e59f0340 LDR r0,|L1.1120|
;;;274 pISR_UNDEF = (unsigned)HaltUndef;
00011c e59f1340 LDR r1,|L1.1124|
000120 e5810f04 STR r0,[r1,#0xf04]
;;;275 pISR_SWI = (unsigned)HaltSwi;
000124 e59f033c LDR r0,|L1.1128|
000128 e5810f08 STR r0,[r1,#0xf08]
;;;276 pISR_PABORT = (unsigned)HaltPabort;
00012c e59f0338 LDR r0,|L1.1132|
000130 e5810f0c STR r0,[r1,#0xf0c]
;;;277 pISR_DABORT = (unsigned)HaltDabort;
000134 e59f0334 LDR r0,|L1.1136|
000138 e5810f10 STR r0,[r1,#0xf10]
;;;278
;;;279 rINTMOD = 0x0; //All=IRQ mode
00013c e3a00000 MOV r0,#0
000140 e3a0144a MOV r1,#0x4a000000
000144 e5810004 STR r0,[r1,#4]
;;;280 // rINTCON=0x5; //Non-vectored,IRQ enable,FIQ disable
;;;281 rINTMSK = BIT_ALLMSK; //All interrupt is masked.
000148 e3e00000 MVN r0,#0
00014c e3a0144a MOV r1,#0x4a000000
000150 e5810008 STR r0,[r1,#8]
;;;282 rINTSUBMSK = BIT_SUB_ALLMSK; //All sub-interrupt is masked. <- April 01, 2002 SOP
000154 e1a008a0 MOV r0,r0,LSR #17
000158 e3a0144a MOV r1,#0x4a000000
00015c e581001c STR r0,[r1,#0x1c]
;;;283
;;;284 // rINTSUBMSK = ~(BIT_SUB_RXD0); //Enable Rx0 Default value=0x7ff
;;;285 // rINTMSK = ~(BIT_UART0); //Enable UART0 Default value=0xffffffff
;;;286
;;;287 // pISR_UART0=(unsigned)RxInt; //pISR_FIQ,pISR_IRQ must be initialized
;;;288 }
000160 e1a0f00e MOV pc,lr
ENDP
xmain PROC
;;;123 void xmain(void)
;;;124 {
000164 e92d40f0 STMFD sp!,{r4-r7,lr}
000168 e24dd024 SUB sp,sp,#0x24
;;;125 int i, voltage=120;
00016c e3a05078 MOV r5,#0x78
;;;126 unsigned int mpll_val;
;;;127
;;;128 // GPIO port init.
;;;129 Port_Init();
000170 ebfffffe BL Port_Init
;;;130
;;;131 Led_Display(0xf);
000174 e3a0000f MOV r0,#0xf
000178 ebfffffe BL Led_Display
;;;132
;;;133 // MMU init. I/D cache on.
;;;134 MMU_Init();
00017c ebfffffe BL MMU_Init
;;;135
;;;136 Led_Display(0x1);
000180 e3a00001 MOV r0,#1
000184 ebfffffe BL Led_Display
;;;137
;;;138 //////// user can set clock again. /////////
;;;139 #if 0
;;;140 Delay(0);
;;;141 voltage=110;
;;;142 Max1718_Set(voltage); // set proper voltage after clock changed.
;;;143 Delay(1);
;;;144
;;;145 #if FIN==12000000 //When 12MHz.
;;;146 ChangeUPllValue(56,2,2); // 48MHz
;;;147 for(i=0; i<7; i++);
;;;148 ChangeClockDivider(13,12);
;;;149 ChangeMPllValue(68,1,1); //2442x
;;;150 #else // else xtal_in=16.9344MHz.
;;;151 ChangeUPllValue(60,4,2); // 48MHz
;;;152 for(i=0; i<7; i++);
;;;153 ChangeClockDivider(13,12);
;;;154 //ChangeMPllValue(118,2,2); //265Mhz
;;;155 ChangeMPllValue(97,1,2); //295Mhz
;;;156 //ChangeMPllValue(110,3,1); //398Mhz
;;;157 //ChangeMPllValue(120,2,1); //531Mhz
;;;158 #endif
;;;159 #endif
;;;160 /////////////////////////////////////////
;;;161
;;;162 Led_Display(0x2);
000188 e3a00002 MOV r0,#2
00018c ebfffffe BL Led_Display
;;;163
;;;164 Calc_Clock(0);
000190 e3a00000 MOV r0,#0
000194 ebfffffe BL Calc_Clock
;;;165 UPDATE_REFRESH(Hclk);
000198 e59f02d4 LDR r0,|L1.1140|
00019c e5900000 LDR r0,[r0,#0] ; Hclk
0001a0 ebfffffe BL _ffltu
0001a4 e1a06000 MOV r6,r0
0001a8 ebfffffe BL _f2d
0001ac e58d000c STR r0,[sp,#0xc]
0001b0 e58d1010 STR r1,[sp,#0x10]
0001b4 e28f0faf ADR r0,|L1.1144|
0001b8 e890000c LDMIA r0,{r2,r3}
0001bc e59d000c LDR r0,[sp,#0xc]
0001c0 ebfffffe BL _dmul
0001c4 e58d0014 STR r0,[sp,#0x14]
0001c8 e58d1018 STR r1,[sp,#0x18]
0001cc e28f0fab ADR r0,|L1.1152|
0001d0 e890000c LDMIA r0,{r2,r3}
0001d4 e59d0014 LDR r0,[sp,#0x14]
0001d8 ebfffffe BL _ddiv
0001dc e58d001c STR r0,[sp,#0x1c]
0001e0 e58d1020 STR r1,[sp,#0x20]
0001e4 ebfffffe BL _dfixu
0001e8 e2600001 RSB r0,r0,#1
0001ec e2800e80 ADD r0,r0,#0x800
0001f0 e3a01448 MOV r1,#0x48000000
0001f4 e5911024 LDR r1,[r1,#0x24]
0001f8 e1a015a1 MOV r1,r1,LSR #11
0001fc e1a01581 MOV r1,r1,LSL #11
000200 e1800001 ORR r0,r0,r1
000204 e3a01448 MOV r1,#0x48000000
000208 e5810024 STR r0,[r1,#0x24]
;;;166
;;;167 // ISR init
;;;168 Isr_Init();
00020c ebfffffe BL Isr_Init
;;;169 Uart_Init(Pclk, 115200);
000210 e59f1270 LDR r1,|L1.1160|
000214 e59f0270 LDR r0,|L1.1164|
000218 e5900000 LDR r0,[r0,#0] ; Pclk
00021c ebfffffe BL Uart_Init
;;;170 Uart_Select(1);
000220 e3a00001 MOV r0,#1
000224 ebfffffe BL Uart_Select
;;;171 Uart_TxEmpty(1);
000228 e3a00001 MOV r0,#1
00022c ebfffffe BL Uart_TxEmpty
;;;172
;;;173 // timer setting for delay 100us unit.
;;;174 //Check whether or not the POWER_OFF wake-up.
;;;175 Delay(0); //calibrate Delay()
000230 e3a00000 MOV r0,#0
000234 ebfffffe BL Delay
;;;176
;;;177 //Turn on LCD.
;;;178 PWR_Lcd_Tft_16Bit_240320_On();
000238 ebfffffe BL PWR_Lcd_Tft_16Bit_240320_On
;;;179
;;;180 //Check_SleepWakeUp(); //It's needed only for sleep mode test.
;;;181
;;;182
;;;183 //Save the wasted power consumption on GPIO.
;;;184 //rIISPSR=(2<<5)|(2<<0); //IIS_LRCK=44.1Khz @384fs,PCLK=50Mhz.
;;;185
;;;186 // Set I/O strength control.
;;;187 rDSC0 = (0<<31)|(0x3<<8)|(0xff<<0);
00023c e59f024c LDR r0,|L1.1168|
000240 e3a01456 MOV r1,#0x56000000
000244 e58100c4 STR r0,[r1,#0xc4]
;;;188 // rDSC0 = (0<<31)|(0x0<<8)|(0x00<<0);
;;;189 // nEN_DSC [31] : 0:I/O drive strength enable, 1:Disable
;;;190 // DSC_ADR [9:8] : Addr drive strength, 0:10mA, 1:8mA, 2:6mA, 3:4mA
;;;191 // DSC_DATA [7:0] : DATA drive strength, 0:12mA, 1:10mA, 2:8mA, 3:6mA
;;;192 rDSC1 = (0x3<<28)|(0x3<<26)|(0xfffff<<0);
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