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📄 user_test2.txt

📁 SMDK2442所有设备的驱动测试程序。运行monitor程序
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; generated by ARM C Compiler, ADS1.2 [Build 805]

; commandline [-errors .\err\User_Test2.err -O0 -asm -g+ -cpu ARM920T -fs "-IC:\Program Files\ARM\ADSv1_2\INCLUDE"]
                          CODE32

                          AREA ||.text||, CODE, READONLY

                  User_Test2 PROC
;;;23     void User_Test2(void)
;;;24     {
000000  e92d4008          STMFD    sp!,{r3,lr}
;;;25     	Uart_Printf("\nUser_Test2.\n");	
000004  e28f0004          ADR      r0,|L1.16|
000008  ebfffffe          BL       Uart_Printf
;;;26     
;;;27     	
;;;28     }
00000c  e8bd8008          LDMFD    sp!,{r3,pc}
                  |L1.16|
000010  6573550a          DCB      "\nUse"
000014  65545f72          DCB      "r_Te"
000018  2e327473          DCB      "st2."
00001c  0000000a          DCB      "\n\0\0\0"
                          ENDP

                  DvsTimer0_intr PROC
;;;216    void __irq DvsTimer0_intr(void)
;;;217    {
000020  e92d0003          STMFD    sp!,{r0,r1}
;;;218    	ClearPending(BIT_TIMER0)
000024  e3a00e40          MOV      r0,#0x400
000028  e3a0144a          MOV      r1,#0x4a000000
00002c  e5810000          STR      r0,[r1,#0]
000030  e3a00e40          MOV      r0,#0x400
000034  e3a0144a          MOV      r1,#0x4a000000
000038  e5810010          STR      r0,[r1,#0x10]
00003c  e3a0044a          MOV      r0,#0x4a000000
000040  e5900010          LDR      r0,[r0,#0x10]
;;;219    }
000044  e8bd0003          LDMFD    sp!,{r0,r1}
000048  e25ef004          SUBS     pc,lr,#4
                          ENDP

                  DvsTimer_Setting PROC
;;;180    void DvsTimer_Setting(void)
;;;181    {
00004c  e92d4010          STMFD    sp!,{r4,lr}
;;;182    	float cnt_val=0.0;
000050  e3a04000          MOV      r4,#0
;;;183    
;;;184        Uart_Printf("[ Timer 0 Interrupt setting]\n");
000054  e28f008c          ADR      r0,|L1.232|
000058  ebfffffe          BL       Uart_Printf
;;;185    
;;;186    	// Uart_Printf("[Timer interval: %4.1f, %4.1f, %4.1f, %4.1f[ms].\n", \
;;;187    	// timer_val_arr[0]*0.081, timer_val_arr[1]*0.081, timer_val_arr[2]*0.081, timer_val_arr[3]*0.081);
;;;188    	// 296, 617, 802, 1284 -> 24ms, 50ms, 65ms, 104ms for eac
;;;189    
;;;190    	rGPBCON = rGPBCON& ~(0x03) | 0x2;
00005c  e3a00456          MOV      r0,#0x56000000
000060  e5900010          LDR      r0,[r0,#0x10]
000064  e3c00003          BIC      r0,r0,#3
000068  e3800002          ORR      r0,r0,#2
00006c  e3a01456          MOV      r1,#0x56000000
000070  e5810010          STR      r0,[r1,#0x10]
;;;191    	rCLKCON |= 1<<8;	// PWM timer PCLK clock enable.
000074  e3a0044c          MOV      r0,#0x4c000000
000078  e590000c          LDR      r0,[r0,#0xc]
00007c  e3800f40          ORR      r0,r0,#0x100
000080  e3a0144c          MOV      r1,#0x4c000000
000084  e581000c          STR      r0,[r1,#0xc]
;;;192    
;;;193    	pISR_TIMER0 = (int)DvsTimer0_intr;
000088  e59f0078          LDR      r0,|L1.264|
00008c  e59f1078          LDR      r1,|L1.268|
000090  e5810f48          STR      r0,[r1,#0xf48]
;;;194    	// Timer interupt start.
;;;195    	rINTMSK &= ~BIT_TIMER0;
000094  e3a0044a          MOV      r0,#0x4a000000
000098  e5900008          LDR      r0,[r0,#8]
00009c  e3c00e40          BIC      r0,r0,#0x400
0000a0  e3a0144a          MOV      r1,#0x4a000000
0000a4  e5810008          STR      r0,[r1,#8]
;;;196    	
;;;197    	rTCFG0 = 0xff;		// Prescaler0 = 0xff=256.
0000a8  e3a000ff          MOV      r0,#0xff
0000ac  e3a01451          MOV      r1,#0x51000000
0000b0  e5810000          STR      r0,[r1,#0]
;;;198    	// Timer input clock freq = PCLK/(Prescaler0+1)/divider value.
;;;199    	// where, PCLK = 50.7MHz
;;;200    
;;;201    	rTCFG1 = 0<<20 | 3<<0;	// MUX0 = 1/16
0000b4  e3a00003          MOV      r0,#3
0000b8  e3a01451          MOV      r1,#0x51000000
0000bc  e5810004          STR      r0,[r1,#4]
;;;202    
;;;203    	// Timer input clock frequency = PCLK/(prescaler value+1)/(divider value)
;;;204    	// 1clock = 81us.
;;;205    	rTCNTB0 = 300;// 296, 617, 802, 1284 -> 24ms, 50ms, 65ms, 104ms for each.
0000c0  e3a00f4b          MOV      r0,#0x12c
0000c4  e3a01451          MOV      r1,#0x51000000
0000c8  e581000c          STR      r0,[r1,#0xc]
;;;206    	rTCMPB0 = 0;
0000cc  e3a00000          MOV      r0,#0
0000d0  e3a01451          MOV      r1,#0x51000000
0000d4  e5810010          STR      r0,[r1,#0x10]
;;;207    
;;;208    	// Load timer cnt value
;;;209    	rTCON = 1<<3| 1<<1;
0000d8  e3a0000a          MOV      r0,#0xa
0000dc  e3a01451          MOV      r1,#0x51000000
0000e0  e5810008          STR      r0,[r1,#8]
;;;210    
;;;211    	// Timer start.
;;;212    	//rTCON = 1<<3| 1<<0;
;;;213    
;;;214    }
0000e4  e8bd8010          LDMFD    sp!,{r4,pc}
                  |L1.232|
0000e8  6954205b          DCB      "[ Ti"
0000ec  2072656d          DCB      "mer "
0000f0  6e492030          DCB      "0 In"
0000f4  72726574          DCB      "terr"
0000f8  20747075          DCB      "upt "
0000fc  74746573          DCB      "sett"
000100  5d676e69          DCB      "ing]"
000104  0000000a          DCB      "\n\0\0\0"
                  |L1.264|
000108  00000000          DCD      DvsTimer0_intr
                  |L1.268|
00010c  31fff000          DCD      0x31fff000
                          ENDP

                  Firm_DVS_Onoff PROC
;;;43     void Firm_DVS_Onoff(void)
;;;44     {
000110  e92d4070          STMFD    sp!,{r4-r6,lr}
000114  e24dd018          SUB      sp,sp,#0x18
;;;45     	volatile int i, n, cnt=0;
000118  e3a00000          MOV      r0,#0
00011c  e1a05000          MOV      r5,r0
;;;46     	
;;;47     	Uart_Printf("DVS test.\n");
000120  e28f0f94          ADR      r0,|L1.888|
000124  ebfffffe          BL       Uart_Printf
;;;48     
;;;49     	rBANKSIZE = (rBANKSIZE & ~(3<<4)) | (0<<4) | (1<<7);	//SCKE_EN, SCLK_EN = disable.
000128  e3a00448          MOV      r0,#0x48000000
00012c  e5900028          LDR      r0,[r0,#0x28]
000130  e3c00030          BIC      r0,r0,#0x30
000134  e3800080          ORR      r0,r0,#0x80
000138  e3a01448          MOV      r1,#0x48000000
00013c  e5810028          STR      r0,[r1,#0x28]
;;;50     
;;;51     	Uart_Printf("Change core speed to 400MHz.\n");
000140  e28f0f8f          ADR      r0,|L1.900|
000144  ebfffffe          BL       Uart_Printf
;;;52     	#if FIN==12000000
;;;53     		ChangeClockDivider(13, 12);
;;;54     		#if CPU2442A==1
;;;55     		ChangeMPllValue(127,2,1);	// 406MHz
;;;56     		#else
;;;57     		ChangeMPllValue(127,2,0);	// 406MHz
;;;58     		#endif
;;;59     	#else	// 16.9344Mhz
;;;60     	ChangeClockDivider(13, 12);
000148  e3a0100c          MOV      r1,#0xc
00014c  e3a0000d          MOV      r0,#0xd
000150  ebfffffe          BL       ChangeClockDivider
;;;61     		#if CPU2442A==1
;;;62     		ChangeMPllValue(110,3,1);	// 400MHz
000154  e3a02001          MOV      r2,#1
000158  e3a01003          MOV      r1,#3
00015c  e3a0006e          MOV      r0,#0x6e
000160  ebfffffe          BL       ChangeMPllValue
;;;63     		#else
;;;64     		ChangeMPllValue(110,3,0);	// 400MHz
;;;65     		#endif
;;;66     	#endif
;;;67     	
;;;68     	Calc_Clock(1);
000164  e3a00001          MOV      r0,#1
000168  ebfffffe          BL       Calc_Clock
;;;69     	
;;;70     	UPDATE_REFRESH(Hclk);
00016c  e59f0230          LDR      r0,|L1.932|
000170  e5900000          LDR      r0,[r0,#0]  ; Hclk
000174  ebfffffe          BL       _ffltu
000178  e1a06000          MOV      r6,r0
00017c  ebfffffe          BL       _f2d
000180  e88d0003          STMIA    sp,{r0,r1}
000184  e28f0f87          ADR      r0,|L1.936|
000188  e890000c          LDMIA    r0,{r2,r3}
00018c  e59d0000          LDR      r0,[sp,#0]
000190  ebfffffe          BL       _dmul
000194  e58d0008          STR      r0,[sp,#8]
000198  e58d100c          STR      r1,[sp,#0xc]
00019c  e28f0f83          ADR      r0,|L1.944|
0001a0  e890000c          LDMIA    r0,{r2,r3}
0001a4  e59d0008          LDR      r0,[sp,#8]
0001a8  ebfffffe          BL       _ddiv
0001ac  e58d0010          STR      r0,[sp,#0x10]
0001b0  e58d1014          STR      r1,[sp,#0x14]
0001b4  ebfffffe          BL       _dfixu
0001b8  e2600001          RSB      r0,r0,#1
0001bc  e2800e80          ADD      r0,r0,#0x800
0001c0  e3a01448          MOV      r1,#0x48000000
0001c4  e5911024          LDR      r1,[r1,#0x24]
0001c8  e1a015a1          MOV      r1,r1,LSR #11
0001cc  e1a01581          MOV      r1,r1,LSL #11
0001d0  e1800001          ORR      r0,r0,r1
0001d4  e3a01448          MOV      r1,#0x48000000
0001d8  e5810024          STR      r0,[r1,#0x24]
;;;71     	Uart_Init(Pclk, 115200);
0001dc  e59f11d4          LDR      r1,|L1.952|
0001e0  e59f01d4          LDR      r0,|L1.956|
0001e4  e5900000          LDR      r0,[r0,#0]  ; Pclk
0001e8  ebfffffe          BL       Uart_Init
;;;72     
;;;73     	Uart_Printf("Check Clkout0:FCLK, Clkout1:HCLK.\n");
0001ec  e28f0f73          ADR      r0,|L1.960|
0001f0  ebfffffe          BL       Uart_Printf
;;;74     	// Clkout0: FCLK.	
;;;75     	Clk0_Enable(2);	// 0:MPLLin, 1:UPLL, 2:FCLK, 3:HCLK, 4:PCLK, 5:DCLK0
0001f4  e3a00002          MOV      r0,#2
0001f8  ebfffffe          BL       Clk0_Enable
;;;76     	// Clkout1: HCLK.
;;;77     	Clk1_Enable(3);	// 0:MPLLout, 1:UPLL, 2:RTC, 3:HCLK, 4:PCLK, 5:DCLK1	
0001fc  e3a00003          MOV      r0,#3
000200  ebfffffe          BL       Clk1_Enable
;;;78     	
;;;79     	DvsTimer_Setting();
000204  ebfffffe          BL       DvsTimer_Setting
;;;80     	
;;;81     	Uart_Printf("start.\n");
000208  e28f0f75          ADR      r0,|L1.996|
00020c  ebfffffe          BL       Uart_Printf
;;;82     
;;;83     	while(1) {
000210  e1a00000          NOP      
                  |L1.532|
000214  e1a00000          NOP      
;;;84     #if 1
;;;85     		// 1. Entering Idle mode ...
;;;86     		// (1) Strengthen HCLK.
;;;87     		rCAMDIVN = (rCAMDIVN & ~(3<<8)) | (1<<8);	// 1:3:6 -> 1:6:12
000218  e3a0044c          MOV      r0,#0x4c000000
00021c  e5900018          LDR      r0,[r0,#0x18]
000220  e3c00fc0          BIC      r0,r0,#0x300
000224  e3800f40          ORR      r0,r0,#0x100
000228  e3a0144c          MOV      r1,#0x4c000000
00022c  e5810018          STR      r0,[r1,#0x18]
;;;88     		rCLKDIVN &= ~(1<<0);						// 1:6:12 -> 1:6:6
000230  e3a0044c          MOV      r0,#0x4c000000
000234  e5900014          LDR      r0,[r0,#0x14]
000238  e3c00001          BIC      r0,r0,#1
00023c  e3a0144c          MOV      r1,#0x4c000000
000240  e5810014          STR      r0,[r1,#0x14]
;;;89     
;;;90     		// (2) Set DVS flag
;;;91     		rCAMDIVN |= BIT_DVS_ON;					// (1<<12)
000244  e3a0044c          MOV      r0,#0x4c000000
000248  e5900018          LDR      r0,[r0,#0x18]
00024c  e3800d40          ORR      r0,r0,#0x1000
000250  e3a0144c          MOV      r1,#0x4c000000
000254  e5810018          STR      r0,[r1,#0x18]
;;;92     		// -> the FCLK will be the same as HCLK(67Mhz).
;;;93     
;;;94     		// (3) Drop the core voltage
;;;95     		Max1718_Set(DVS_VOLTL);
000258  e3a00050          MOV      r0,#0x50
00025c  ebfffffe          BL       Max1718_Set
;;;96     
;;;97     
;;;98     		// (4) t_DVS, delay while dropping the core voltage...
;;;99     		//for(i=0; i<2000; i++);		// SMDK2442: 28us/0.1V.
;;;100    
;;;101    		// (5) set Idle bit.
;;;102    		// timer setting...
;;;103    		rTCNTB0 = 30;
000260  e3a0001e          MOV      r0,#0x1e
000264  e3a01451          MOV      r1,#0x51000000
000268  e581000c          STR      r0,[r1,#0xc]
;;;104    		rTCON = 1<<3| 1<<1;	// load timer.
00026c  e3a0000a          MOV      r0,#0xa
000270  e3a01451          MOV      r1,#0x51000000
000274  e5810008          STR      r0,[r1,#8]
;;;105    		rTCON = 1<<3| 1<<0;	// start timer.
000278  e3a00009          MOV      r0,#9
00027c  e3a01451          MOV      r1,#0x51000000
000280  e5810008          STR      r0,[r1,#8]
;;;106    
;;;107    		rCLKCON |= 1<<2;	// Enter Idle mode.
000284  e3a0044c          MOV      r0,#0x4c000000
000288  e590000c          LDR      r0,[r0,#0xc]
00028c  e3800004          ORR      r0,r0,#4
000290  e3a0144c          MOV      r1,#0x4c000000
000294  e581000c          STR      r0,[r1,#0xc]
;;;108    		for(i=0;i<10;i++);
000298  e3a00000          MOV      r0,#0
00029c  e1a04000          MOV      r4,r0
                  |L1.672|
0002a0  e354000a          CMP      r4,#0xa
0002a4  aa000002          BGE      |L1.692|
0002a8  e2840001          ADD      r0,r4,#1
0002ac  e1a04000          MOV      r4,r0
0002b0  eafffffa          B        |L1.672|
;;;109    
;;;110    		//...
;;;111    		//... in Idle mode...
;;;112    		//...
;;;113    
;;;114    		// 2. Wake up from Idle mode...
;;;115    		rCLKCON&=~(1<<2);		// must clear this bit after wake-up from idle mode.
                  |L1.692|
0002b4  e3a0044c          MOV      r0,#0x4c000000

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