📄 uart0.txt
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0006b8 e59f0368 LDR r0,|L1.2600|
0006bc e5900000 LDR r0,[r0,#0] ; Fclk
0006c0 e59f1378 LDR r1,|L1.2624|
0006c4 e0400001 SUB r0,r0,r1
0006c8 e59f1374 LDR r1,|L1.2628|
0006cc e1500001 CMP r0,r1
0006d0 2a000018 BCS |L1.1848|
;;;169 {
;;;170 rUCON0 = (rUCON0 & ~(0xf<<12)) | (0xe<<12); // FCLK divider 14(n=20), for max 921.6kbps
0006d4 e3a00450 MOV r0,#0x50000000
0006d8 e5900004 LDR r0,[r0,#4]
0006dc e3c00cf0 BIC r0,r0,#0xf000
0006e0 e3800ce0 ORR r0,r0,#0xe000
0006e4 e3a01450 MOV r1,#0x50000000
0006e8 e5810004 STR r0,[r1,#4]
;;;171 rUCON1 &= ~(0xf<<12); // 0 setting
0006ec e2810c40 ADD r0,r1,#0x4000
0006f0 e5900004 LDR r0,[r0,#4]
0006f4 e3c00cf0 BIC r0,r0,#0xf000
0006f8 e2811c40 ADD r1,r1,#0x4000
0006fc e5810004 STR r0,[r1,#4]
;;;172 rUCON2 &= ~(0xf<<12); // 0 setting
000700 e2810c40 ADD r0,r1,#0x4000
000704 e5900004 LDR r0,[r0,#4]
000708 e3c00cf0 BIC r0,r0,#0xf000
00070c e2811c40 ADD r1,r1,#0x4000
000710 e5810004 STR r0,[r1,#4]
;;;173 clock = Fclk / 20;
000714 e59f030c LDR r0,|L1.2600|
000718 e5901000 LDR r1,[r0,#0] ; Fclk
00071c e3a00014 MOV r0,#0x14
000720 ebfffffe BL __rt_udiv
000724 e1a04000 MOV r4,r0
;;;174 Uart_Printf("1 : %d\n", clock);
000728 e1a01004 MOV r1,r4
00072c e28f0fc5 ADR r0,|L1.2632|
000730 ebfffffe BL Uart_Printf
000734 ea00003d B |L1.2096|
;;;175 }
;;;176 else if ( (Fclk>395000000) && (Fclk<405000000) ) // for 399MHz
|L1.1848|
000738 e59f02e8 LDR r0,|L1.2600|
00073c e5900000 LDR r0,[r0,#0] ; Fclk
000740 e59f1308 LDR r1,|L1.2640|
000744 e0400001 SUB r0,r0,r1
000748 e59f12f4 LDR r1,|L1.2628|
00074c e1500001 CMP r0,r1
000750 2a000018 BCS |L1.1976|
;;;177 {
;;;178 rUCON1 = (rUCON1 & ~(0xf<<12)) | (0x6<<12); // FCLK divider 6(n=27), for max 921.6kbps
000754 e51f02d8 LDR r0,|L1.1156|
000758 e5900004 LDR r0,[r0,#4]
00075c e3c00cf0 BIC r0,r0,#0xf000
000760 e3800c60 ORR r0,r0,#0x6000
000764 e51f12e8 LDR r1,|L1.1156|
000768 e5810004 STR r0,[r1,#4]
;;;179 rUCON0 &= ~(0xf<<12); // 0 setting
00076c e3a00450 MOV r0,#0x50000000
000770 e5900004 LDR r0,[r0,#4]
000774 e3c00cf0 BIC r0,r0,#0xf000
000778 e3a01450 MOV r1,#0x50000000
00077c e5810004 STR r0,[r1,#4]
;;;180 rUCON2 &= ~(0xf<<12); // 0 setting
000780 e2810c80 ADD r0,r1,#0x8000
000784 e5900004 LDR r0,[r0,#4]
000788 e3c00cf0 BIC r0,r0,#0xf000
00078c e2811c80 ADD r1,r1,#0x8000
000790 e5810004 STR r0,[r1,#4]
;;;181 clock = Fclk / 27;
000794 e59f028c LDR r0,|L1.2600|
000798 e5901000 LDR r1,[r0,#0] ; Fclk
00079c e3a0001b MOV r0,#0x1b
0007a0 ebfffffe BL __rt_udiv
0007a4 e1a04000 MOV r4,r0
;;;182 Uart_Printf("2 : %d\n", clock);
0007a8 e1a01004 MOV r1,r4
0007ac e28f0fa8 ADR r0,|L1.2644|
0007b0 ebfffffe BL Uart_Printf
0007b4 ea00001d B |L1.2096|
;;;183 }
;;;184 else if ( (Fclk>525000000) && (Fclk<535000000) ) // for 530MHz
|L1.1976|
0007b8 e59f0268 LDR r0,|L1.2600|
0007bc e5900000 LDR r0,[r0,#0] ; Fclk
0007c0 e59f1294 LDR r1,|L1.2652|
0007c4 e0400001 SUB r0,r0,r1
0007c8 e59f1274 LDR r1,|L1.2628|
0007cc e1500001 CMP r0,r1
0007d0 2a000016 BCS |L1.2096|
;;;185 {
;;;186 rUCON1 |= (0xf<<12); // FCLK divider 15(n=36), for max. 921.6kbps
0007d4 e51f0358 LDR r0,|L1.1156|
0007d8 e5900004 LDR r0,[r0,#4]
0007dc e3800cf0 ORR r0,r0,#0xf000
0007e0 e51f1364 LDR r1,|L1.1156|
0007e4 e5810004 STR r0,[r1,#4]
;;;187 rUCON0 &= ~(0xf<<12); // 0 setting
0007e8 e3a00450 MOV r0,#0x50000000
0007ec e5900004 LDR r0,[r0,#4]
0007f0 e3c00cf0 BIC r0,r0,#0xf000
0007f4 e3a01450 MOV r1,#0x50000000
0007f8 e5810004 STR r0,[r1,#4]
;;;188 rUCON2 &= ~(0xf<<12); // 0 setting
0007fc e2810c80 ADD r0,r1,#0x8000
000800 e5900004 LDR r0,[r0,#4]
000804 e3c00cf0 BIC r0,r0,#0xf000
000808 e2811c80 ADD r1,r1,#0x8000
00080c e5810004 STR r0,[r1,#4]
;;;189 clock = Fclk / 36;
000810 e59f0210 LDR r0,|L1.2600|
000814 e5901000 LDR r1,[r0,#0] ; Fclk
000818 e3a00024 MOV r0,#0x24
00081c ebfffffe BL __rt_udiv
000820 e1a04000 MOV r4,r0
;;;190 Uart_Printf("3 : %d\n", clock);
000824 e1a01004 MOV r1,r4
000828 e28f0f8c ADR r0,|L1.2656|
00082c ebfffffe BL Uart_Printf
;;;191 }
;;;192 rUCON2 |= (1<<15); // enable FCLK/n
|L1.2096|
000830 e51f03a0 LDR r0,|L1.1176|
000834 e5900004 LDR r0,[r0,#4]
000838 e3800c80 ORR r0,r0,#0x8000
00083c e51f13ac LDR r1,|L1.1176|
000840 e5810004 STR r0,[r1,#4]
;;;193 #else
;;;194 // In 921.6kbps case of following code, Fclk must be 296352000
;;;195 rUCON0 = rUCON0 & ~(0xf<<12) | (0xe<<12); // FCLK divider 14(n=20), for max 921.6kbps
;;;196 rUCON1 &= ~(0xf<<12); // 0 setting
;;;197 rUCON2 &= ~(0xf<<12); // 0 setting
;;;198 clock = Fclk / 20;
;;;199 rUCON2 |= (1<<15); // enable FCLK/n
;;;200 #endif
;;;201
;;;202 // select buadrate.
;;;203 if(ch == 0) {
000844 e3560000 CMP r6,#0
000848 1a000021 BNE |L1.2260|
;;;204 rUCON0 |= (3<<10); // Select FCLK/n
00084c e3a00450 MOV r0,#0x50000000
000850 e5900004 LDR r0,[r0,#4]
000854 e3800ec0 ORR r0,r0,#0xc00
000858 e3a01450 MOV r1,#0x50000000
00085c e5810004 STR r0,[r1,#4]
;;;205 rUBRDIV0=( (int)(clock/16./baud+0.5) -1 ); //Baud rate divisior register
000860 e1a00004 MOV r0,r4
000864 ebfffffe BL _dflt
000868 e88d0003 STMIA sp,{r0,r1}
00086c e24f0fef ADR r0,|L1.1208|
000870 e890000c LDMIA r0,{r2,r3}
000874 e59d0000 LDR r0,[sp,#0]
000878 ebfffffe BL _dmul
00087c e58d0010 STR r0,[sp,#0x10]
000880 e58d1014 STR r1,[sp,#0x14]
000884 e1a00005 MOV r0,r5
000888 ebfffffe BL _dflt
00088c e58d0008 STR r0,[sp,#8]
000890 e58d100c STR r1,[sp,#0xc]
000894 e59d2010 LDR r2,[sp,#0x10]
000898 e59d3014 LDR r3,[sp,#0x14]
00089c ebfffffe BL _drdiv
0008a0 e58d0018 STR r0,[sp,#0x18]
0008a4 e58d101c STR r1,[sp,#0x1c]
0008a8 e24f0f89 ADR r0,|L1.1676|
0008ac e890000c LDMIA r0,{r2,r3}
0008b0 e59d0018 LDR r0,[sp,#0x18]
0008b4 ebfffffe BL _dadd
0008b8 e58d0020 STR r0,[sp,#0x20]
0008bc e58d1024 STR r1,[sp,#0x24]
0008c0 ebfffffe BL _dfix
0008c4 e2400001 SUB r0,r0,#1
0008c8 e3a01450 MOV r1,#0x50000000
0008cc e5810028 STR r0,[r1,#0x28]
0008d0 ea000044 B |L1.2536|
;;;206 }
;;;207 else if(ch==1){
|L1.2260|
0008d4 e3560001 CMP r6,#1
0008d8 1a000021 BNE |L1.2404|
;;;208 rUCON1 |= (3<<10); // Select FCLK/n
0008dc e51f0460 LDR r0,|L1.1156|
0008e0 e5900004 LDR r0,[r0,#4]
0008e4 e3800ec0 ORR r0,r0,#0xc00
0008e8 e51f146c LDR r1,|L1.1156|
0008ec e5810004 STR r0,[r1,#4]
;;;209 rUBRDIV1=( (int)(clock/16./baud+0.5) -1 ); //Baud rate divisior register
0008f0 e1a00004 MOV r0,r4
0008f4 ebfffffe BL _dflt
0008f8 e88d0003 STMIA sp,{r0,r1}
0008fc e59f0164 LDR r0,|L1.2664|
000900 e890000c LDMIA r0,{r2,r3}
000904 e59d0000 LDR r0,[sp,#0]
000908 ebfffffe BL _dmul
00090c e58d0010 STR r0,[sp,#0x10]
000910 e58d1014 STR r1,[sp,#0x14]
000914 e1a00005 MOV r0,r5
000918 ebfffffe BL _dflt
00091c e58d0008 STR r0,[sp,#8]
000920 e58d100c STR r1,[sp,#0xc]
000924 e59d2010 LDR r2,[sp,#0x10]
000928 e59d3014 LDR r3,[sp,#0x14]
00092c ebfffffe BL _drdiv
000930 e58d0018 STR r0,[sp,#0x18]
000934 e58d101c STR r1,[sp,#0x1c]
000938 e24f0fad ADR r0,|L1.1676|
00093c e890000c LDMIA r0,{r2,r3}
000940 e59d0018 LDR r0,[sp,#0x18]
000944 ebfffffe BL _dadd
000948 e58d0020 STR r0,[sp,#0x20]
00094c e58d1024 STR r1,[sp,#0x24]
000950 ebfffffe BL _dfix
000954 e2400001 SUB r0,r0,#1
000958 e51f14dc LDR r1,|L1.1156|
00095c e5810028 STR r0,[r1,#0x28]
000960 ea000020 B |L1.2536|
;;;210 }
;;;211 else {
;;;212 rUCON2 |= (3<<10); // Select FCLK/n
|L1.2404|
000964 e51f04d4 LDR r0,|L1.1176|
000968 e5900004 LDR r0,[r0,#4]
00096c e3800ec0 ORR r0,r0,#0xc00
000970 e51f14e0 LDR r1,|L1.1176|
000974 e5810004 STR r0,[r1,#4]
;;;213 rUBRDIV2=( (int)(clock/16./baud+0.5) -1 ); //Baud rate divisior register
000978 e1a00004 MOV r0,r4
00097c ebfffffe BL _dflt
000980 e88d0003 STMIA sp,{r0,r1}
000984 e59f00dc LDR r0,|L1.2664|
000988 e890000c LDMIA r0,{r2,r3}
00098c e59d0000 LDR r0,[sp,#0]
000990 ebfffffe BL _dmul
000994 e58d0010 STR r0,[sp,#0x10]
000998 e58d1014 STR r1,[sp,#0x14]
00099c e1a00005 MOV r0,r5
0009a0 ebfffffe BL _dflt
0009a4 e58d0008 STR r0,[sp,#8]
0009a8 e58d100c STR r1,[sp,#0xc]
0009ac e59d2010 LDR r2,[sp,#0x10]
0009b0 e59d3014 LDR r3,[sp,#0x14]
0009b4 ebfffffe BL _drdiv
0009b8 e58d0018 STR r0,[sp,#0x18]
0009bc e58d101c STR r1,[sp,#0x1c]
0009c0 e24f0fcf ADR r0,|L1.1676|
0009c4 e890000c LDMIA r0,{r2,r3}
0009c8 e59d0018 LDR r0,[sp,#0x18]
0009cc ebfffffe BL _dadd
0009d0 e58d0020 STR r0,[sp,#0x20]
0009d4 e58d1024 STR r1,[sp,#0x24]
0009d8 ebfffffe BL _dfix
0009dc e2400001 SUB r0,r0,#1
0009e0 e51f1550 LDR r1,|L1.1176|
0009e4 e5810028 STR r0,[r1,#0x28]
;;;214 }
;;;215
;;;216 // S/W work-around for using FCLK/n
;;;217 rGPHCON = rGPHCON & ~(3<<16); //GPH8(UEXTCLK) input
|L1.2536|
0009e8 e3a00456 MOV r0,#0x56000000
0009ec e5900070 LDR r0,[r0,#0x70]
0009f0 e3c00bc0 BIC r0,r0,#0x30000
0009f4 e3a01456 MOV r1,#0x56000000
0009f8 e5810070 STR r0,[r1,#0x70]
;;;218 Delay(1);
0009fc e3a00001 MOV r0,#1
000a00 ebfffffe BL Delay
;;;219 rGPHCON = rGPHCON & ~(3<<16) | (1<<17); //GPH8(UEXTCLK) UEXTCLK
000a04 e3a00456 MOV r0,#0x56000000
000a08 e5900070 LDR r0,[r0,#0x70]
000a0c e3c00bc0 BIC r0,r0,#0x30000
000a10 e3800b80 ORR r0,r0,#0x20000
000a14 e3a01456 MOV r1,#0x56000000
000a18 e5810070 STR r0,[r1,#0x70]
;;;220 }
000a1c e28dd028 ADD sp,sp,#0x28
000a20 e8bd8070 LDMFD sp!,{r4-r6,pc}
|L1.2596|
000a24 02f1a980 DCD 0x02f1a980
|L1.2600|
000a28 00000000 DCD Fclk
|L1.2604|
000a2c 72727543 DCB "Curr"
000a30 20746e65 DCB "ent "
000a34 4b4c4346 DCB "FCLK"
000a38 20736920 DCB " is "
000a3c 000a6425 DCB "%d\n\0"
|L1.2624|
000a40 11490c81 DCD 0x11490c81
|L1.2628|
000a44 0098967f DCD 0x0098967f
|L1.2632|
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