📄 uart0.txt
字号:
00033c ebfffffe BL _dflt
000340 e58d0008 STR r0,[sp,#8]
000344 e58d100c STR r1,[sp,#0xc]
000348 e59d2010 LDR r2,[sp,#0x10]
00034c e59d3014 LDR r3,[sp,#0x14]
000350 ebfffffe BL _drdiv
000354 e58d0018 STR r0,[sp,#0x18]
000358 e58d101c STR r1,[sp,#0x1c]
00035c ebfffffe BL _dfix
000360 e2400001 SUB r0,r0,#1
000364 e3a01450 MOV r1,#0x50000000
000368 e5810028 STR r0,[r1,#0x28]
00036c ea00003a B |L1.1116|
;;;133 }
;;;134 else if(ch==1){
|L1.880|
000370 e3560001 CMP r6,#1
000374 1a00001c BNE |L1.1004|
;;;135 rUCON1 = rUCON1 & ~(1<<11) |(1<<10); // Select UEXTCLK
000378 e59f0104 LDR r0,|L1.1156|
00037c e5900004 LDR r0,[r0,#4]
000380 e3c00e80 BIC r0,r0,#0x800
000384 e3800e40 ORR r0,r0,#0x400
000388 e59f10f4 LDR r1,|L1.1156|
00038c e5810004 STR r0,[r1,#4]
;;;136 rUBRDIV1=( (int)(clock/16./baud) -1 ); //Baud rate divisior register
000390 e1a00005 MOV r0,r5
000394 ebfffffe BL _dflt
000398 e88d0003 STMIA sp,{r0,r1}
00039c e28f0f45 ADR r0,|L1.1208|
0003a0 e890000c LDMIA r0,{r2,r3}
0003a4 e59d0000 LDR r0,[sp,#0]
0003a8 ebfffffe BL _dmul
0003ac e58d0010 STR r0,[sp,#0x10]
0003b0 e58d1014 STR r1,[sp,#0x14]
0003b4 e1a00004 MOV r0,r4
0003b8 ebfffffe BL _dflt
0003bc e58d0008 STR r0,[sp,#8]
0003c0 e58d100c STR r1,[sp,#0xc]
0003c4 e59d2010 LDR r2,[sp,#0x10]
0003c8 e59d3014 LDR r3,[sp,#0x14]
0003cc ebfffffe BL _drdiv
0003d0 e58d0018 STR r0,[sp,#0x18]
0003d4 e58d101c STR r1,[sp,#0x1c]
0003d8 ebfffffe BL _dfix
0003dc e2400001 SUB r0,r0,#1
0003e0 e59f109c LDR r1,|L1.1156|
0003e4 e5810028 STR r0,[r1,#0x28]
0003e8 ea00001b B |L1.1116|
;;;137 }
;;;138 else {
;;;139 rUCON2 = rUCON2 & ~(1<<11) |(1<<10); // Select UEXTCLK
|L1.1004|
0003ec e59f00a4 LDR r0,|L1.1176|
0003f0 e5900004 LDR r0,[r0,#4]
0003f4 e3c00e80 BIC r0,r0,#0x800
0003f8 e3800e40 ORR r0,r0,#0x400
0003fc e59f1094 LDR r1,|L1.1176|
000400 e5810004 STR r0,[r1,#4]
;;;140 rUBRDIV2=( (int)(clock/16./baud) -1 ); //Baud rate divisior register
000404 e1a00005 MOV r0,r5
000408 ebfffffe BL _dflt
00040c e88d0003 STMIA sp,{r0,r1}
000410 e28f00a0 ADR r0,|L1.1208|
000414 e890000c LDMIA r0,{r2,r3}
000418 e59d0000 LDR r0,[sp,#0]
00041c ebfffffe BL _dmul
000420 e58d0010 STR r0,[sp,#0x10]
000424 e58d1014 STR r1,[sp,#0x14]
000428 e1a00004 MOV r0,r4
00042c ebfffffe BL _dflt
000430 e58d0008 STR r0,[sp,#8]
000434 e58d100c STR r1,[sp,#0xc]
000438 e59d2010 LDR r2,[sp,#0x10]
00043c e59d3014 LDR r3,[sp,#0x14]
000440 ebfffffe BL _drdiv
000444 e58d0018 STR r0,[sp,#0x18]
000448 e58d101c STR r1,[sp,#0x1c]
00044c ebfffffe BL _dfix
000450 e2400001 SUB r0,r0,#1
000454 e59f103c LDR r1,|L1.1176|
000458 e5810028 STR r0,[r1,#0x28]
;;;141 }
;;;142 }
|L1.1116|
00045c e28dd020 ADD sp,sp,#0x20
000460 e8bd8070 LDMFD sp!,{r4-r6,pc}
|L1.1124|
000464 00000050 DCD ||.bss$2|| + 80
|L1.1128|
000468 00000054 DCD ||.bss$2|| + 84
|L1.1132|
00046c 00000058 DCD ||.bss$2|| + 88
|L1.1136|
000470 0002aaaa DCD 0x0002aaaa
|L1.1140|
000474 0000005c DCD ||.bss$2|| + 92
|L1.1144|
000478 00000060 DCD ||.bss$2|| + 96
|L1.1148|
00047c 00000064 DCD ||.bss$2|| + 100
|L1.1152|
000480 00000068 DCD ||.bss$2|| + 104
|L1.1156|
000484 50004000 DCD 0x50004000
|L1.1160|
000488 00000070 DCD ||.bss$2|| + 112
|L1.1164|
00048c 00000074 DCD ||.bss$2|| + 116
|L1.1168|
000490 00000078 DCD ||.bss$2|| + 120
|L1.1172|
000494 0000007c DCD ||.bss$2|| + 124
|L1.1176|
000498 50008000 DCD 0x50008000
|L1.1180|
00049c 00000084 DCD ||.bss$2|| + 132
|L1.1184|
0004a0 00000088 DCD ||.bss$2|| + 136
|L1.1188|
0004a4 0000008c DCD ||.bss$2|| + 140
|L1.1192|
0004a8 00000090 DCD ||.bss$2|| + 144
|L1.1196|
0004ac 0000006c DCD ||.bss$2|| + 108
|L1.1200|
0004b0 00000080 DCD ||.bss$2|| + 128
|L1.1204|
0004b4 00000094 DCD ||.bss$2|| + 148
|L1.1208|
0004b8 00000000 DCFD 0x3fb0000000000000
0004bc 3fb00000
ENDP
Uart_Pclk_En PROC
;;;145 void Uart_Pclk_En(int ch, int baud)
;;;146 {
0004c0 e92d4030 STMFD sp!,{r4,r5,lr}
0004c4 e24dd02c SUB sp,sp,#0x2c
0004c8 e1a05000 MOV r5,r0
0004cc e1a04001 MOV r4,r1
;;;147 if(ch == 0) {
0004d0 e3550000 CMP r5,#0
0004d4 1a000022 BNE |L1.1380|
;;;148 rUCON0 &= ~(3<<10); // Select PCLK
0004d8 e3a00450 MOV r0,#0x50000000
0004dc e5900004 LDR r0,[r0,#4]
0004e0 e3c00ec0 BIC r0,r0,#0xc00
0004e4 e3a01450 MOV r1,#0x50000000
0004e8 e5810004 STR r0,[r1,#4]
;;;149 rUBRDIV0=( (int)(Pclk/16./baud+0.5) -1 ); //Baud rate divisior register
0004ec e59f0194 LDR r0,|L1.1672|
0004f0 e5900000 LDR r0,[r0,#0] ; Pclk
0004f4 ebfffffe BL _dfltu
0004f8 e98d0003 STMIB sp,{r0,r1}
0004fc e24f004c ADR r0,|L1.1208|
000500 e890000c LDMIA r0,{r2,r3}
000504 e59d0004 LDR r0,[sp,#4]
000508 ebfffffe BL _dmul
00050c e58d0014 STR r0,[sp,#0x14]
000510 e58d1018 STR r1,[sp,#0x18]
000514 e1a00004 MOV r0,r4
000518 ebfffffe BL _dflt
00051c e58d000c STR r0,[sp,#0xc]
000520 e58d1010 STR r1,[sp,#0x10]
000524 e59d2014 LDR r2,[sp,#0x14]
000528 e59d3018 LDR r3,[sp,#0x18]
00052c ebfffffe BL _drdiv
000530 e58d001c STR r0,[sp,#0x1c]
000534 e58d1020 STR r1,[sp,#0x20]
000538 e28f0f53 ADR r0,|L1.1676|
00053c e890000c LDMIA r0,{r2,r3}
000540 e59d001c LDR r0,[sp,#0x1c]
000544 ebfffffe BL _dadd
000548 e58d0024 STR r0,[sp,#0x24]
00054c e58d1028 STR r1,[sp,#0x28]
000550 ebfffffe BL _dfix
000554 e2400001 SUB r0,r0,#1
000558 e3a01450 MOV r1,#0x50000000
00055c e5810028 STR r0,[r1,#0x28]
000560 ea000046 B |L1.1664|
;;;150 }
;;;151 else if(ch==1){
|L1.1380|
000564 e3550001 CMP r5,#1
000568 1a000022 BNE |L1.1528|
;;;152 rUCON1 &= ~(3<<10); // Select PCLK
00056c e51f00f0 LDR r0,|L1.1156|
000570 e5900004 LDR r0,[r0,#4]
000574 e3c00ec0 BIC r0,r0,#0xc00
000578 e51f10fc LDR r1,|L1.1156|
00057c e5810004 STR r0,[r1,#4]
;;;153 rUBRDIV1=( (int)(Pclk/16./baud+0.5) -1 ); //Baud rate divisior register
000580 e59f0100 LDR r0,|L1.1672|
000584 e5900000 LDR r0,[r0,#0] ; Pclk
000588 ebfffffe BL _dfltu
00058c e98d0003 STMIB sp,{r0,r1}
000590 e24f00e0 ADR r0,|L1.1208|
000594 e890000c LDMIA r0,{r2,r3}
000598 e59d0004 LDR r0,[sp,#4]
00059c ebfffffe BL _dmul
0005a0 e58d0014 STR r0,[sp,#0x14]
0005a4 e58d1018 STR r1,[sp,#0x18]
0005a8 e1a00004 MOV r0,r4
0005ac ebfffffe BL _dflt
0005b0 e58d000c STR r0,[sp,#0xc]
0005b4 e58d1010 STR r1,[sp,#0x10]
0005b8 e59d2014 LDR r2,[sp,#0x14]
0005bc e59d3018 LDR r3,[sp,#0x18]
0005c0 ebfffffe BL _drdiv
0005c4 e58d001c STR r0,[sp,#0x1c]
0005c8 e58d1020 STR r1,[sp,#0x20]
0005cc e28f00b8 ADR r0,|L1.1676|
0005d0 e890000c LDMIA r0,{r2,r3}
0005d4 e59d001c LDR r0,[sp,#0x1c]
0005d8 ebfffffe BL _dadd
0005dc e58d0024 STR r0,[sp,#0x24]
0005e0 e58d1028 STR r1,[sp,#0x28]
0005e4 ebfffffe BL _dfix
0005e8 e2400001 SUB r0,r0,#1
0005ec e51f1170 LDR r1,|L1.1156|
0005f0 e5810028 STR r0,[r1,#0x28]
0005f4 ea000021 B |L1.1664|
;;;154 }
;;;155 else {
;;;156 rUCON2 &= ~(3<<10); // Select PCLK
|L1.1528|
0005f8 e51f0168 LDR r0,|L1.1176|
0005fc e5900004 LDR r0,[r0,#4]
000600 e3c00ec0 BIC r0,r0,#0xc00
000604 e51f1174 LDR r1,|L1.1176|
000608 e5810004 STR r0,[r1,#4]
;;;157 rUBRDIV2=( (int)(Pclk/16./baud+0.5) -1 ); //Baud rate divisior register
00060c e59f0074 LDR r0,|L1.1672|
000610 e5900000 LDR r0,[r0,#0] ; Pclk
000614 ebfffffe BL _dfltu
000618 e98d0003 STMIB sp,{r0,r1}
00061c e24f0f5b ADR r0,|L1.1208|
000620 e890000c LDMIA r0,{r2,r3}
000624 e59d0004 LDR r0,[sp,#4]
000628 ebfffffe BL _dmul
00062c e58d0014 STR r0,[sp,#0x14]
000630 e58d1018 STR r1,[sp,#0x18]
000634 e1a00004 MOV r0,r4
000638 ebfffffe BL _dflt
00063c e58d000c STR r0,[sp,#0xc]
000640 e58d1010 STR r1,[sp,#0x10]
000644 e59d2014 LDR r2,[sp,#0x14]
000648 e59d3018 LDR r3,[sp,#0x18]
00064c ebfffffe BL _drdiv
000650 e58d001c STR r0,[sp,#0x1c]
000654 e58d1020 STR r1,[sp,#0x20]
000658 e28f002c ADR r0,|L1.1676|
00065c e890000c LDMIA r0,{r2,r3}
000660 e59d001c LDR r0,[sp,#0x1c]
000664 ebfffffe BL _dadd
000668 e58d0024 STR r0,[sp,#0x24]
00066c e58d1028 STR r1,[sp,#0x28]
000670 ebfffffe BL _dfix
000674 e2400001 SUB r0,r0,#1
000678 e51f11e8 LDR r1,|L1.1176|
00067c e5810028 STR r0,[r1,#0x28]
;;;158 }
;;;159 }
|L1.1664|
000680 e28dd02c ADD sp,sp,#0x2c
000684 e8bd8030 LDMFD sp!,{r4,r5,pc}
|L1.1672|
000688 00000000 DCD Pclk
|L1.1676|
00068c 00000000 DCFD 0x3fe0000000000000 ; 0.5
000690 3fe00000
ENDP
Uart_Fclkn_En PROC
;;;161 void Uart_Fclkn_En(int ch, int baud) // for 2442A
;;;162 {
000694 e92d4070 STMFD sp!,{r4-r6,lr}
000698 e24dd028 SUB sp,sp,#0x28
00069c e1a06000 MOV r6,r0
0006a0 e1a05001 MOV r5,r1
;;;163 int clock = PCLK;//Pclk;
0006a4 e59f4378 LDR r4,|L1.2596|
;;;164
;;;165 Uart_Printf("Current FCLK is %d\n", Fclk);
0006a8 e59f0378 LDR r0,|L1.2600|
0006ac e5901000 LDR r1,[r0,#0] ; Fclk
0006b0 e28f0fdd ADR r0,|L1.2604|
0006b4 ebfffffe BL Uart_Printf
;;;166 #if 1
;;;167 // input clock divider setting.
;;;168 if ( (Fclk>290000000) && (Fclk<300000000) ) // for 296MHz
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