📄 sleep.txt
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000880 e3a00000 MOV r0,#0
000884 e3a01457 MOV r1,#0x57000000
000888 e5c10088 STRB r0,[r1,#0x88]
;;;322 rBCDMON = TESTMONTH;
00088c e3a00012 MOV r0,#0x12
000890 e3a01457 MOV r1,#0x57000000
000894 e5c10084 STRB r0,[r1,#0x84]
;;;323 rBCDDAY = TESTDAY; // SUN:1 MON:2 TUE:3 WED:4 THU:5 FRI:6 SAT:7
000898 e3a00006 MOV r0,#6
00089c e3a01457 MOV r1,#0x57000000
0008a0 e5c10080 STRB r0,[r1,#0x80]
;;;324 rBCDDATE = TESTDATE;
0008a4 e3a00031 MOV r0,#0x31
0008a8 e3a01457 MOV r1,#0x57000000
0008ac e5c1007c STRB r0,[r1,#0x7c]
;;;325 rBCDHOUR = TESTHOUR;
0008b0 e3a00023 MOV r0,#0x23
0008b4 e3a01457 MOV r1,#0x57000000
0008b8 e5c10078 STRB r0,[r1,#0x78]
;;;326 rBCDMIN = TESTMIN;
0008bc e3a00059 MOV r0,#0x59
0008c0 e3a01457 MOV r1,#0x57000000
0008c4 e5c10074 STRB r0,[r1,#0x74]
;;;327 rBCDSEC = TESTSEC;
0008c8 e3a00059 MOV r0,#0x59
0008cc e3a01457 MOV r1,#0x57000000
0008d0 e5c10070 STRB r0,[r1,#0x70]
;;;328
;;;329 rALMYEAR=TESTYEAR2 ;
0008d4 e3a00001 MOV r0,#1
0008d8 e3a01457 MOV r1,#0x57000000
0008dc e5c10068 STRB r0,[r1,#0x68]
;;;330 rALMMON =TESTMONTH2;
0008e0 e3a00001 MOV r0,#1
0008e4 e3a01457 MOV r1,#0x57000000
0008e8 e5c10064 STRB r0,[r1,#0x64]
;;;331 rALMDATE=TESTDATE2 ;
0008ec e3a00001 MOV r0,#1
0008f0 e3a01457 MOV r1,#0x57000000
0008f4 e5c10060 STRB r0,[r1,#0x60]
;;;332 rALMHOUR=TESTHOUR2 ;
0008f8 e3a00000 MOV r0,#0
0008fc e3a01457 MOV r1,#0x57000000
000900 e5c1005c STRB r0,[r1,#0x5c]
;;;333 rALMMIN =TESTMIN2 ;
000904 e3a00000 MOV r0,#0
000908 e3a01457 MOV r1,#0x57000000
00090c e5c10058 STRB r0,[r1,#0x58]
;;;334 rALMSEC =TESTSEC2+3;
000910 e3a00003 MOV r0,#3
000914 e3a01457 MOV r1,#0x57000000
000918 e5c10054 STRB r0,[r1,#0x54]
;;;335
;;;336 rRTCALM=0x7f;
00091c e3a0007f MOV r0,#0x7f
000920 e3a01457 MOV r1,#0x57000000
000924 e5c10050 STRB r0,[r1,#0x50]
;;;337
;;;338 rRTCCON=0x0; // R/W disable, 1/32768, Normal(merge), No reset
000928 e3a00000 MOV r0,#0
00092c e3a01457 MOV r1,#0x57000000
000930 e5c10040 STRB r0,[r1,#0x40]
;;;339 }
000934 e1a0f00e MOV pc,lr
ENDP
ConfigMiscIO PROC
;;;344 void ConfigMiscIO(void)
;;;345 {
000938 e3a00456 MOV r0,#0x56000000
;;;346 // memory data/control signal pin status definition when sleep.
;;;347 mslcon_bak = rMSLCON;
00093c e59000cc LDR r0,[r0,#0xcc]
000940 e59f124c LDR r1,|L1.2964|
000944 e5810000 STR r0,[r1,#0] ; mslcon_bak
;;;348
;;;349 // In the evaluation board, Even though in sleep mode, the devices are all supplied the power.
;;;350 //rMSLCON = (0<<11)|(0<<10)|(0<<9)|(0<<8)|(0<<7)|(0<<6)|(0<<5)|(0<<4)|(0<<3)|(0<<2)|(0<<1)|(0<<0);
;;;351 rMSLCON = (1<<11)|(0<<10)|(0<<9)|(1<<8)|(1<<7)|(1<<6)|(1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|(1<<0);
000948 e59f0248 LDR r0,|L1.2968|
00094c e3a01456 MOV r1,#0x56000000
000950 e58100cc STR r0,[r1,#0xcc]
;;;352 //rMSLCON = (0<<11)|(0<<10)|(0<<9)|(1<<8)|(1<<7)|(1<<6)|(1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|(1<<0);
;;;353
;;;354 // Memory interface signal definition when sleep mode.
;;;355 //PSC_DATA [11] DATA status, 0:output "0" ( All 32-bit data Low drive ), 1:Hi-Z
;;;356 //PSC_WAIT [10] nWAIT status, 0:output "0", 1: input
;;;357 //PSC_RnB [9] RnB status, 0:output "0", 1: input
;;;358 //PSC_NF [8] NAND Flash I/O status, 0:inactive nFCE,nFRE,nFWE,ALE,CLE = 11100, 1: Hi-Z
;;;359 //PSC_SDR [7] nSRAS, nSCAS status, 0:inactive( "11"), 1: Hi-Z
;;;360 //PSC_DQM [6] DQM[3:0]/nWE[3:0] status, 0:inactive( "0000"), 1:Hi-Z
;;;361 //PSC_OE [5] nOE status, 0:inactive( "1"), 1:Hi-Z
;;;362 //PSC_WE [4] nWE status, 0:inactive( "1"), 1:Hi-Z
;;;363 //PSC_GCS0 [3] nGCS[0] status, 0:inactive( "1"), 1:Hi-Z
;;;364 //PSC_GCS[5:1][2] nGCS[5:1] status, 0:inactive( "1"), 1:Hi-Z
;;;365 //PSC_GCS6 [1] nGCS[6] status, 0:inactive( "1"), 1:Hi-Z
;;;366 //PSC_GCS7 [0] nGCS[7] status, 0:inactive( "1"), 1:Hi-Z
;;;367
;;;368 #if 1 // 0:*1, 1:*2.
;;;369 //Uart_Printf("Drive strength control(*2).\n");
;;;370
;;;371 dsc0_bak = rDSC0;
000954 e3a00456 MOV r0,#0x56000000
000958 e59000c4 LDR r0,[r0,#0xc4]
00095c e59f1238 LDR r1,|L1.2972|
000960 e5810000 STR r0,[r1,#0] ; dsc0_bak
;;;372 dsc1_bak = rDSC1;
000964 e3a00456 MOV r0,#0x56000000
000968 e59000c8 LDR r0,[r0,#0xc8]
00096c e59f122c LDR r1,|L1.2976|
000970 e5810000 STR r0,[r1,#0] ; dsc1_bak
;;;373
;;;374 rDSC0 = 0x7fffffff;
000974 e3e00480 MVN r0,#0x80000000
000978 e3a01456 MOV r1,#0x56000000
00097c e58100c4 STR r0,[r1,#0xc4]
;;;375 rDSC0 &= ~(1<<31); //enable
000980 e3a00456 MOV r0,#0x56000000
000984 e59000c4 LDR r0,[r0,#0xc4]
000988 e3c00480 BIC r0,r0,#0x80000000
00098c e3a01456 MOV r1,#0x56000000
000990 e58100c4 STR r0,[r1,#0xc4]
;;;376 // nEN_DSC [31] Enable Drive strength control, 0:enable
;;;377 // DSC_ADR [9:8] Address bus drive strength. 0:10mA, 1:8mA, 2:6mA, 3:4mA
;;;378 // DSC_DATA [7:0] Data bus drive strength, 0:12mA, 1:10mA, 2:8mA, 3:6mA
;;;379 //rDSC1 = (3<<28)|(3<<26)|(3<24)|(3<<22)|(3<<20)|(3<<18);
;;;380 rDSC1 = 0x7fffffff;
000994 e3e00480 MVN r0,#0x80000000
000998 e3a01456 MOV r1,#0x56000000
00099c e58100c8 STR r0,[r1,#0xc8]
;;;381
;;;382 // 0:16mA, 1:12mA, 2:8mA, 3:6mA
;;;383 //DSC_SCK1 [29:28] SCLK1
;;;384 //DSC_SCK0 [27:26] SCLK0
;;;385 //DSC_SCKE [25:24] SCKE
;;;386 //DSC_SDR [23:22] nSRAS/nSCAS
;;;387 //DSC_NFC [21:20] Nand Flash(nFCWE, nFRE, nFWE,CLE,ALE) Control
;;;388 //DSC_BE [19:18] nBE[3:0]
;;;389 //DSC_WOE [17:16] nWE/nOE
;;;390 //DSC_CS7 [15:14] nGCS7
;;;391 //DSC_CS6 [13:12] nGCS6
;;;392 //DSC_CS5 [11:10] nGCS5
;;;393 //DSC_CS4 [9:8] nGCS4
;;;394 //DSC_CS3 [7:6] nGCS3
;;;395 //DSC_CS2 [5:4] nGCS2
;;;396 //DSC_CS1 [3:2] nGCS1
;;;397 //DSC_CS0 [1:0] nGCS0
;;;398 #else
;;;399 //Uart_Printf("Drive strength control(*1).\n");
;;;400 rDSC0 |= (1<<31); //disable
;;;401
;;;402 rDSC0 = (1<<31)|(3<<8)|(3<<0);
;;;403 // nEN_DSC [31] Enable Drive strength control, 1:enable
;;;404 // DSC_ADR [9:8] Address bus drive strength. 0:10mA, 1:8mA, 2:6mA, 3:4mA
;;;405 // DSC_DATA [7:0] Data bus drive strength, 0:12mA, 1:10mA, 2:8mA, 3:6mA
;;;406 rDSC1 = (3<<28)|(3<<26)|(3<24)|(3<<22)|(3<<20)|(3<<18);
;;;407 #endif
;;;408
;;;409 }
0009a0 e1a0f00e MOV pc,lr
ENDP
Test_SleepMode PROC
;;;462 void Test_SleepMode(void)
;;;463 {
0009a4 e92d4038 STMFD sp!,{r3-r5,lr}
;;;464 int i, mode, error=0;
0009a8 e3a05000 MOV r5,#0
;;;465 U32 portStatus[33+3];
;;;466
;;;467 Uart_Printf("[Sleep Mode Test]\n");
0009ac e28f0f7c ADR r0,|L1.2980|
0009b0 ebfffffe BL Uart_Printf
;;;468
;;;469 //Added for battery fault...
;;;470 #if 0
;;;471 Uart_Printf("nBATT_FLT pin should be tested.\n");
;;;472 Uart_Printf("\nBattery fault interrupt setting.\n");
;;;473 Uart_Printf("Detect low-level.\n");
;;;474
;;;475 Uart_Printf("0 : Reset system during nBATT_FLT=0.\n");
;;;476 Uart_Printf("4 : System will be wake-up from sleep mode during nBATT_FLT=0.\n");
;;;477 Uart_Printf("6 : System will ignore Eint0 signal during nBATT_FLT=0.\n");
;;;478 Uart_Printf("7 : Disable Battery function.\n");
;;;479 Uart_Printf("Select battery function : ");
;;;480 i = Uart_GetIntNum() & 0x7;
;;;481
;;;482 rMISCCR = (rMISCCR & ~(0x1f<<20)) | (i<<20);
;;;483 // [22:20]
;;;484 // if 0, System will be Reset during nBATT_FLT=0.
;;;485 // if 4, System will be wake-up from sleep mode during nBATT_FLT=0.
;;;486 // if 6, System will ignore nBATT_FLT signal.
;;;487 // if 7, Disable Battery function.
;;;488
;;;489 Uart_Printf("rMISCCR0:%x\n", rMISCCR);
;;;490
;;;491 rMISCCR |=(0x67<<3);
;;;492
;;;493 Uart_Printf("rMISCCR1:%x\n", rMISCCR);
;;;494
;;;495 pISR_BAT_FLT = (U32)BattFaultInt;
;;;496 rSRCPND = BIT_BAT_FLT;
;;;497 rINTPND = BIT_BAT_FLT;
;;;498
;;;499 rINTMSK = rINTMSK & ~(BIT_BAT_FLT); // unmask.
;;;500
;;;501 #endif
;;;502 //Added for battery fault... End
;;;503
;;;504 #if 0
;;;505 Uart_Printf("Check SDRAM for self-refresh test\n");
;;;506 for(i=_NONCACHE_STARTADDRESS;i<(_NONCACHE_STARTADDRESS+0x400000);i+=4)
;;;507 {
;;;508 //Uart_Printf("%x=%x(%x)\n",i,*((U32 *)i),i^0x55555555);
;;;509 if(*((U32 *)i)!=(i^0x55555555))
;;;510 {
;;;511 Uart_Printf("Mem Error:%x=%x(%x)\n",i,*((U32 *)i),i^0x55555555);
;;;512 error++;
;;;513 }
;;;514 if(error>20)
;;;515 break;
;;;516 }
;;;517 if(error)
;;;518 Uart_Printf("SDRAM self-refresh test:FAILED\n");
;;;519 else
;;;520 Uart_Printf("SDRAM self-refresh test:O.K.\n");
;;;521 #endif
;;;522
;;;523 Uart_TxEmpty(1); //Wait until UART0 Tx buffer empty.
0009b4 e3a00001 MOV r0,#1
0009b8 ebfffffe BL Uart_TxEmpty
;;;524
;;;525 #if 0
;;;526 SelectEintType();
;;;527 #else
;;;528 rGPFCON=rGPFCON & ~(3<<0)|(2<<0); //PF0=EINT0
0009bc e3a00456 MOV r0,#0x56000000
0009c0 e5900050 LDR r0,[r0,#0x50]
0009c4 e3c00003 BIC r0,r0,#3
0009c8 e3800002 ORR r0,r0,#2
0009cc e3a01456 MOV r1,#0x56000000
0009d0 e5810050 STR r0,[r1,#0x50]
;;;529 rEXTINT0=rEXTINT0&~(7<<0)|(2<<0); //EINT0=falling edge triggered
0009d4 e3a00456 MOV r0,#0x56000000
0009d8 e5900088 LDR r0,[r0,#0x88]
0009dc e3c00007 BIC r0,r0,#7
0009e0 e3800002 ORR r0,r0,#2
0009e4 e3a01456 MOV r1,#0x56000000
0009e8 e5810088 STR r0,[r1,#0x88]
;;;530 #endif
;;;531
;;;532 #if 1 //test whether or not the interrupt pending bit retain the wake-up source.
;;;533 pISR_EINT0=(U32)Eint0Int;
0009ec e59f01c4 LDR r0,|L1.3000|
0009f0 e59f11c4 LDR r1,|L1.3004|
0009f4 e5810f20 STR r0,[r1,#0xf20]
;;;534 pISR_EINT8_23=(U32)Eint8_23Int;
0009f8 e59f01c0 LDR r0,|L1.3008|
0009fc e5810f34 STR r0,[r1,#0xf34]
;;;535 pISR_RTC=(U32)AlarmInt;
000a00 e59f01bc LDR r0,|L1.3012|
000a04 e5810f98 STR r0,[r1,#0xf98]
;;;536
;;;537 rINTMSK = ~(BIT_EINT0|BIT_EINT8_23|BIT_RTC);
000a08 e3e00185 MVN r0,#0x40000021
000a0c e3a0144a MOV r1,#0x4a000000
000a10 e5810008 STR r0,[r1,#8]
;;;538
;;;539 for(i=0;i<100;i++);
000a14 e3a04000 MOV r4,#0
|L1.2584|
000a18 e3540064 CMP r4,#0x64
000a1c aa000001 BGE |L1.2600|
000a20 e2844001 ADD r4,r4,#1
000a24 eafffffb B |L1.2584|
;;;540
;;;541 rSRCPND = BIT_EINT0|BIT_EINT8_23|BIT_RTC;
|L1.2600|
000a28 e3a00185 MOV r0,#0x40000021
000a2c e3a0144a MOV r1,#0x4a000000
000a30 e5810000 STR r0,[r1,#0]
;;;542 rINTPND = BIT_EINT0|BIT_EINT8_23|BIT_RTC;
000a34 e3a00185 MOV r0,#0x40000021
000a38 e3a0144a MOV r1,#0x4a000000
000a3c e5810010 STR r0,[r1,#0x10]
;;;543
;;;544 rEINTPEND=rEINTPEND;
000a40 e3a00456 MOV r0,#0x56000000
000a44 e59000a8 LDR r0,[r0,#0xa8]
000a48 e3a01456 MOV r1,#0x56000000
000a4c e58100a8 STR r0,[r1,#0xa8]
;;;545 rSRCPND=rSRCPND;
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