📄 cpuspeed.txt
字号:
; generated by ARM C Compiler, ADS1.2 [Build 805]
; commandline [-errors .\err\CpuSpeed.err -O0 -asm -g+ -cpu ARM920T -fs "-IC:\Program Files\ARM\ADSv1_2\INCLUDE"]
CODE32
AREA ||.text||, CODE, READONLY
CpuSpeedFunc1 PROC
;;;156 void CpuSpeedFunc1(void)
;;;157 {
000000 e92d4038 STMFD sp!,{r3-r5,lr}
;;;158 int i,j;
;;;159 i=0;
000004 e3a04000 MOV r4,#0
;;;160
;;;161
;;;162 for(i=0;i<10;i++) {
000008 e3a04000 MOV r4,#0
|L1.12|
00000c e354000a CMP r4,#0xa
000010 aa000015 BGE |L1.108|
000014 ea000001 B |L1.32|
|L1.24|
000018 e2844001 ADD r4,r4,#1
00001c eafffffa B |L1.12|
;;;163 LED_DISPLAY(i%16);
|L1.32|
000020 e1e00004 MVN r0,r4
000024 e1a01fc0 MOV r1,r0,ASR #31
000028 e0801e21 ADD r1,r0,r1,LSR #28
00002c e1a01241 MOV r1,r1,ASR #4
000030 e0401201 SUB r1,r0,r1,LSL #4
000034 e201000f AND r0,r1,#0xf
000038 e3a01456 MOV r1,#0x56000000
00003c e5911054 LDR r1,[r1,#0x54]
000040 e3c110f0 BIC r1,r1,#0xf0
000044 e1810200 ORR r0,r1,r0,LSL #4
000048 e3a01456 MOV r1,#0x56000000
00004c e5810054 STR r0,[r1,#0x54]
;;;164 for(j=0;j<600000;j++);
000050 e3a05000 MOV r5,#0
|L1.84|
000054 e255ca90 SUBS r12,r5,#0x90000
000058 a25ccd9f SUBGES r12,r12,#0x27c0
00005c aa000001 BGE |L1.104|
000060 e2855001 ADD r5,r5,#1
000064 eafffffa B |L1.84|
;;;165 }
|L1.104|
000068 eaffffea B |L1.24|
;;;166
;;;167 //The following code should not use the stack memory.
;;;168 // because the stack memory is not DCache-locked.
;;;169 // It's should be checked using disassembly code.
;;;170
;;;171 #if 1
;;;172 // Set clock frequency.
;;;173 ChangeClockDivider(14,12);
|L1.108|
00006c e3a0100c MOV r1,#0xc
000070 e3a0000e MOV r0,#0xe
000074 ebfffffe BL ChangeClockDivider
;;;174
;;;175 // ChangeMPllValue(0xa1, 0x3,0x1); // FCLK=202MHz
;;;176 // ChangeMPllValue(150, 6, 0); // FCLK=237MHz
;;;177 // ChangeMPllValue(180, 3, 0); // FCLK=451MHz
;;;178 ChangeMPllValue(214, 3, 0); // FCLK=523.8MHz
000078 e3a02000 MOV r2,#0
00007c e3a01003 MOV r1,#3
000080 e3a000d6 MOV r0,#0xd6
000084 ebfffffe BL ChangeMPllValue
;;;179 // ChangeMPllValue(0xa7,0x4,0x0); // FCLK=350MHz
;;;180 // ChangeMPllValue(0x55,0x1,0x0); // FCLK=372MHz
;;;181
;;;182 // ChangeClockDivider(14,12); // 400:100:50
;;;183 // ChangeMPllValue(92,1,0); // FCLK=400MHz
;;;184
;;;185 UPDATE_REFRESH(133000000); // UPDATE_REFRES(HCLK);
000088 e3a00448 MOV r0,#0x48000000
00008c e5900024 LDR r0,[r0,#0x24]
000090 e1a005a0 MOV r0,r0,LSR #11
000094 e1a00580 MOV r0,r0,LSL #11
000098 e3800ffd ORR r0,r0,#0x3f4
00009c e3a01448 MOV r1,#0x48000000
0000a0 e5810024 STR r0,[r1,#0x24]
;;;186
;;;187 #endif
;;;188
;;;189 #if 0
;;;190 rREFRESH |= 1<<22; // SDRAM1 self refresh.
;;;191 #endif
;;;192
;;;193
;;;194 LED_DISPLAY(0x0);
0000a4 e3a00456 MOV r0,#0x56000000
0000a8 e5900054 LDR r0,[r0,#0x54]
0000ac e38000f0 ORR r0,r0,#0xf0
0000b0 e3a01456 MOV r1,#0x56000000
0000b4 e5810054 STR r0,[r1,#0x54]
;;;195
;;;196 while(1) // only for test: caching area
0000b8 e1a00000 NOP
|L1.188|
0000bc e1a00000 NOP
;;;197 {
;;;198 for(i=0;i<0x100;i+=4)
0000c0 e3a04000 MOV r4,#0
|L1.196|
0000c4 e3540f40 CMP r4,#0x100
0000c8 aa000009 BGE |L1.244|
0000cc ea000001 B |L1.216|
|L1.208|
0000d0 e2844004 ADD r4,r4,#4
0000d4 eafffffa B |L1.196|
;;;199 *(volatile U32 *)(TEST_STADDR+i)=0x12345678*i+i; // Write data.
|L1.216|
0000d8 e59f01c0 LDR r0,|L1.672|
0000dc e0010490 MUL r1,r0,r4
0000e0 e0840181 ADD r0,r4,r1,LSL #3
0000e4 e28415c0 ADD r1,r4,#0x30000000
0000e8 e28118f0 ADD r1,r1,#0xf00000
0000ec e5810000 STR r0,[r1,#0]
0000f0 eafffff6 B |L1.208|
;;;200
;;;201 for(i=0;i<0x100;i+=4) {
|L1.244|
0000f4 e3a04000 MOV r4,#0
|L1.248|
0000f8 e3540f40 CMP r4,#0x100
0000fc aa000017 BGE |L1.352|
000100 ea000001 B |L1.268|
|L1.260|
000104 e2844004 ADD r4,r4,#4
000108 eafffffa B |L1.248|
;;;202 if(*(volatile U32 *)(TEST_STADDR+i)!=0x12345678*i+i) { // Error
|L1.268|
00010c e59f018c LDR r0,|L1.672|
000110 e0010490 MUL r1,r0,r4
000114 e0840181 ADD r0,r4,r1,LSL #3
000118 e28415c0 ADD r1,r4,#0x30000000
00011c e28118f0 ADD r1,r1,#0xf00000
000120 e5911000 LDR r1,[r1,#0]
000124 e1500001 CMP r0,r1
000128 0a000007 BEQ |L1.332|
;;;203 LED_DISPLAY(0x5);
00012c e3a00456 MOV r0,#0x56000000
000130 e5900054 LDR r0,[r0,#0x54]
000134 e3c000f0 BIC r0,r0,#0xf0
000138 e38000a0 ORR r0,r0,#0xa0
00013c e3a01456 MOV r1,#0x56000000
000140 e5810054 STR r0,[r1,#0x54]
;;;204 while(1);
000144 e1a00000 NOP
|L1.328|
000148 eafffffe B |L1.328|
;;;205 }
;;;206
;;;207 *(volatile U32 *)(TEST_STADDR+i)=0x0; // Clear memory.
|L1.332|
00014c e3a00000 MOV r0,#0
000150 e28415c0 ADD r1,r4,#0x30000000
000154 e28118f0 ADD r1,r1,#0xf00000
000158 e5810000 STR r0,[r1,#0]
;;;208 }
00015c eaffffe8 B |L1.260|
;;;209
;;;210 LED_DISPLAY(0x0);
|L1.352|
000160 e3a00456 MOV r0,#0x56000000
000164 e5900054 LDR r0,[r0,#0x54]
000168 e38000f0 ORR r0,r0,#0xf0
00016c e3a01456 MOV r1,#0x56000000
000170 e5810054 STR r0,[r1,#0x54]
;;;211
;;;212 i=0;
000174 e3a04000 MOV r4,#0
;;;213 i++;
000178 e2844001 ADD r4,r4,#1
;;;214 i=i*0x12345678; // i=1.
00017c e59f1120 LDR r1,|L1.676|
000180 e0040491 MUL r4,r1,r4
;;;215 if(i==0x12345678) LED_DISPLAY(0x1); //OK.
000184 e1a00001 MOV r0,r1
000188 e1540000 CMP r4,r0
00018c 1a000006 BNE |L1.428|
000190 e3a00456 MOV r0,#0x56000000
000194 e5900054 LDR r0,[r0,#0x54]
000198 e3c000f0 BIC r0,r0,#0xf0
00019c e38000e0 ORR r0,r0,#0xe0
0001a0 e3a01456 MOV r1,#0x56000000
0001a4 e5810054 STR r0,[r1,#0x54]
0001a8 ea000004 B |L1.448|
;;;216 else LED_DISPLAY(0x0);
|L1.428|
0001ac e3a00456 MOV r0,#0x56000000
0001b0 e5900054 LDR r0,[r0,#0x54]
0001b4 e38000f0 ORR r0,r0,#0xf0
0001b8 e3a01456 MOV r1,#0x56000000
0001bc e5810054 STR r0,[r1,#0x54]
;;;217 }
|L1.448|
0001c0 eaffffbd B |L1.188|
;;;218 }
ENDP
CpuSpeedFunc2 PROC
;;;219
;;;220 void CpuSpeedFunc2(void){}
0001c4 e1a0f00e MOV pc,lr
ENDP
Test_CpuSpeed PROC
;;;32 void Test_CpuSpeed(void)
;;;33 {
0001c8 e92d40f8 STMFD sp!,{r3-r7,lr}
;;;34 int i,j,base;
;;;35 U32 uLockPt,bypass;
;;;36
;;;37 // added for testing 2442.
;;;38 Uart_Printf("[CPU Core Speed Test]\n");
0001cc e28f00d4 ADR r0,|L1.680|
0001d0 ebfffffe BL Uart_Printf
;;;39
;;;40 // Set MMU enable and on/off I/D-cache.
;;;41 Uart_Printf("[MMU enable]\n");
0001d4 e28f00e4 ADR r0,|L1.704|
0001d8 ebfffffe BL Uart_Printf
;;;42 MMU_EnableMMU();
0001dc ebfffffe BL MMU_EnableMMU
;;;43 Uart_Printf("[ICache enable]\n");
0001e0 e28f00e8 ADR r0,|L1.720|
0001e4 ebfffffe BL Uart_Printf
;;;44 MMU_EnableICache();
0001e8 ebfffffe BL MMU_EnableICache
;;;45 Uart_Printf("[DCache enable]\n");
0001ec e28f00f0 ADR r0,|L1.740|
0001f0 ebfffffe BL Uart_Printf
;;;46 MMU_EnableDCache(); //DCache should be turned on after MMU is turned on.
0001f4 ebfffffe BL MMU_EnableDCache
;;;47
;;;48 //Uart_Printf("[FCLK:HCLK:PCLK] = [%d:%d:%d]MHz\n", FCLK/1000000, HCLK/1000000, PCLK/1000000);
;;;49 Uart_Printf("DCache locked area: %xH~%xH\n", TEST_STADDR, TEST_ENDADDR);
0001f8 e59f20f8 LDR r2,|L1.760|
0001fc e24210ff SUB r1,r2,#0xff
000200 e28f00f4 ADR r0,|L1.764|
000204 ebfffffe BL Uart_Printf
;;;50 Uart_Printf("ICache locked area: %x~%x(256B boundary)\n",
000208 e59f210c LDR r2,|L1.796|
00020c e59f110c LDR r1,|L1.800|
000210 e28f0f43 ADR r0,|L1.804|
000214 ebfffffe BL Uart_Printf
;;;51 (U32)CpuSpeedFunc1,(U32)CpuSpeedFunc2);
;;;52 Uart_Printf("LCD is disabled.\n");
000218 e28f0f4c ADR r0,|L1.848|
00021c ebfffffe BL Uart_Printf
;;;53 //LCD_DisplayControl(0);
;;;54 rLCDCON1&=~1; // ENVID=OFF
000220 e3a0044d MOV r0,#0x4d000000
000224 e5900000 LDR r0,[r0,#0]
000228 e3c00001 BIC r0,r0,#1
00022c e3a0144d MOV r1,#0x4d000000
000230 e5810000 STR r0,[r1,#0]
;;;55 LED_DISPLAY(0x1); // LED 1
000234 e3a00456 MOV r0,#0x56000000
000238 e5900054 LDR r0,[r0,#0x54]
00023c e3c000f0 BIC r0,r0,#0xf0
000240 e38000e0 ORR r0,r0,#0xe0
000244 e3a01456 MOV r1,#0x56000000
000248 e5810054 STR r0,[r1,#0x54]
;;;56
;;;57 Uart_Printf("<<LED status>>\n");
00024c e28f0f44 ADR r0,|L1.868|
000250 ebfffffe BL Uart_Printf
;;;58 Uart_Printf("(1) LED4 blink: R/W OK.\n");
000254 e28f0f46 ADR r0,|L1.884|
000258 ebfffffe BL Uart_Printf
;;;59 Uart_Printf("(2) LED4 OFF: Multiply error(R/W OK).\n");
00025c e28f0f4b ADR r0,|L1.912|
000260 ebfffffe BL Uart_Printf
;;;60 Uart_Printf("(3) LED4/7 ON: R/W Error.\n");
000264 e28f0f53 ADR r0,|L1.952|
000268 ebfffffe BL Uart_Printf
;;;61
;;;62 Uart_Printf("Cache lock-down.\n");
00026c e28f0f58 ADR r0,|L1.980|
000270 ebfffffe BL Uart_Printf
;;;63
;;;64
;;;65 //========== ICache lock-down ==========
;;;66 MMU_SetICacheLockdownBase(10<<26); // The following code will be filled between cache line 10~63.
000274 e3a005a0 MOV r0,#0x28000000
000278 ebfffffe BL MMU_SetICacheLockdownBase
;;;67 base=10;
00027c e3a0500a MOV r5,#0xa
;;;68 bypass=1;
000280 e3a07001 MOV r7,#1
;;;69 uLockPt=(U32)CpuSpeedFunc1&0xffffffe0;
000284 e59f0094 LDR r0,|L1.800|
000288 e3c0401f BIC r4,r0,#0x1f
;;;70
;;;71 for(;uLockPt<(U32)CpuSpeedFunc2;uLockPt+=0x20)
00028c e1a00000 NOP
|L1.656|
000290 e59f0084 LDR r0,|L1.796|
000294 e1540000 CMP r4,r0
000298 2a000068 BCS |L1.1088|
00029c ea000053 B |L1.1008|
|L1.672|
0002a0 02468acf DCD 0x02468acf
|L1.676|
0002a4 12345678 DCD 0x12345678
|L1.680|
0002a8 5550435b DCB "[CPU"
0002ac 726f4320 DCB " Cor"
0002b0 70532065 DCB "e Sp"
0002b4 20646565 DCB "eed "
0002b8 74736554 DCB "Test"
0002bc 00000a5d DCB "]\n\0\0"
|L1.704|
0002c0 554d4d5b DCB "[MMU"
0002c4 616e6520 DCB " ena"
0002c8 5d656c62 DCB "ble]"
0002cc 0000000a DCB "\n\0\0\0"
|L1.720|
0002d0 6143495b DCB "[ICa"
0002d4 20656863 DCB "che "
0002d8 62616e65 DCB "enab"
0002dc 0a5d656c DCB "le]\n"
0002e0 00000000 DCB "\0\0\0\0"
|L1.740|
0002e4 6143445b DCB "[DCa"
0002e8 20656863 DCB "che "
0002ec 62616e65 DCB "enab"
0002f0 0a5d656c DCB "le]\n"
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -