📄 cslr_dev.h
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/*********************************************************************
* Copyright (C) 2003-2006 Texas Instruments Incorporated.
* All Rights Reserved
*********************************************************************/
/** \file cslr_dev.h
*
* \brief This file contains the Register Desciptions for DEV
*
*********************************************************************/
#ifndef _CSLR_DEV_H_
#define _CSLR_DEV_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 DEVSTAT;
volatile Uint32 PRI_ALLOC;
volatile Uint32 JTAGID;
volatile Uint8 RSVD0[262136];
volatile Uint32 PERLOCK;
volatile Uint32 PERCFG0;
volatile Uint8 RSVD1[8];
volatile Uint32 PERSTAT0;
volatile Uint32 PERSTAT1;
volatile Uint8 RSVD2[4];
volatile Uint32 EMACCFG;
volatile Uint8 RSVD3[8];
volatile Uint32 PERCFG1;
volatile Uint8 RSVD4[36];
volatile Uint32 EMUBUFPDN;
} CSL_DevRegs;
/*
* Overlay structure typedef definition TBR
*/
typedef volatile CSL_DevRegs *CSL_DevRegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* DEVSTAT */
#define CSL_DEV_DEVSTAT_EMIFA_EN_MASK (0x00400000u)
#define CSL_DEV_DEVSTAT_EMIFA_EN_SHIFT (0x00000016u)
#define CSL_DEV_DEVSTAT_EMIFA_EN_RESETVAL (0x00000000u)
/*----EMIFA_EN Tokens----*/
#define CSL_DEV_DEVSTAT_EMIFA_EN_DISABLE (0x00000000u)
#define CSL_DEV_DEVSTAT_EMIFA_EN_ENABLE (0x00000001u)
#define CSL_DEV_DEVSTAT_DDR2_EN_MASK (0x00200000u)
#define CSL_DEV_DEVSTAT_DDR2_EN_SHIFT (0x00000015u)
#define CSL_DEV_DEVSTAT_DDR2_EN_RESETVAL (0x00000000u)
/*----DDR2_EN Tokens----*/
#define CSL_DEV_DEVSTAT_DDR2_EN_DISABLE (0x00000000u)
#define CSL_DEV_DEVSTAT_DDR2_EN_ENABLE (0x00000001u)
#define CSL_DEV_DEVSTAT_PCI_EN_MASK (0x00100000u)
#define CSL_DEV_DEVSTAT_PCI_EN_SHIFT (0x00000014u)
#define CSL_DEV_DEVSTAT_PCI_EN_RESETVAL (0x00000000u)
/*----PCI_EN Tokens----*/
#define CSL_DEV_DEVSTAT_PCI_EN_HPI (0x00000000u)
#define CSL_DEV_DEVSTAT_PCI_EN_PCI (0x00000001u)
#define CSL_DEV_DEVSTAT_CFGGP_MASK (0x000E0000u)
#define CSL_DEV_DEVSTAT_CFGGP_SHIFT (0x00000011u)
#define CSL_DEV_DEVSTAT_CFGGP_RESETVAL (0x00000000u)
#define CSL_DEV_DEVSTAT_SYSCLKOUT_EN_MASK (0x00008000u)
#define CSL_DEV_DEVSTAT_SYSCLKOUT_EN_SHIFT (0x0000000Fu)
#define CSL_DEV_DEVSTAT_SYSCLKOUT_EN_RESETVAL (0x00000000u)
/*----SYSCLKOUT_EN Tokens----*/
#define CSL_DEV_DEVSTAT_SYSCLKOUT_EN_GP1 (0x00000000u)
#define CSL_DEV_DEVSTAT_SYSCLKOUT_EN_SYSCLK4 (0x00000001u)
#define CSL_DEV_DEVSTAT_MCBSP1_EN_MASK (0x00004000u)
#define CSL_DEV_DEVSTAT_MCBSP1_EN_SHIFT (0x0000000Eu)
#define CSL_DEV_DEVSTAT_MCBSP1_EN_RESETVAL (0x00000000u)
/*----MCBSP1_EN Tokens----*/
#define CSL_DEV_DEVSTAT_MCBSP1_EN_GPIO (0x00000000u)
#define CSL_DEV_DEVSTAT_MCBSP1_EN_MCBSP_1 (0x00000001u)
#define CSL_DEV_DEVSTAT_PCI66_MASK (0x00002000u)
#define CSL_DEV_DEVSTAT_PCI66_SHIFT (0x0000000Du)
#define CSL_DEV_DEVSTAT_PCI66_RESETVAL (0x00000000u)
/*----PCI66 Tokens----*/
#define CSL_DEV_DEVSTAT_PCI66_33MHZ (0x00000000u)
#define CSL_DEV_DEVSTAT_PCI66_66MHZ (0x00000001u)
#define CSL_DEV_DEVSTAT_VLYNQ_EN_MASK (0x00001000u)
#define CSL_DEV_DEVSTAT_VLYNQ_EN_SHIFT (0x0000000Cu)
#define CSL_DEV_DEVSTAT_VLYNQ_EN_RESETVAL (0x00000000u)
/*----VLYNQ_EN Tokens----*/
#define CSL_DEV_DEVSTAT_VLYNQ_EN_DISABLE (0x00000000u)
#define CSL_DEV_DEVSTAT_VLYNQ_EN_ENABLE (0x00000001u)
#define CSL_DEV_DEVSTAT_PCI_EEAI_MASK (0x00000800u)
#define CSL_DEV_DEVSTAT_PCI_EEAI_SHIFT (0x0000000Bu)
#define CSL_DEV_DEVSTAT_PCI_EEAI_RESETVAL (0x00000000u)
/*----PCI_EEAI Tokens----*/
#define CSL_DEV_DEVSTAT_PCI_EEAI_DISABLE (0x00000000u)
#define CSL_DEV_DEVSTAT_PCI_EEAI_ENABLE (0x00000001u)
#define CSL_DEV_DEVSTAT_MACSEL_MASK (0x00000600u)
#define CSL_DEV_DEVSTAT_MACSEL_SHIFT (0x00000009u)
#define CSL_DEV_DEVSTAT_MACSEL_RESETVAL (0x00000000u)
/*----MACSEL Tokens----*/
#define CSL_DEV_DEVSTAT_MACSEL_MII (0x00000000u)
#define CSL_DEV_DEVSTAT_MACSEL_RMII (0x00000001u)
#define CSL_DEV_DEVSTAT_MACSEL_GMII (0x00000002u)
#define CSL_DEV_DEVSTAT_MACSEL_RGMII (0x00000003u)
#define CSL_DEV_DEVSTAT_UTOPIA_EN_MASK (0x00000080u)
#define CSL_DEV_DEVSTAT_UTOPIA_EN_SHIFT (0x00000007u)
#define CSL_DEV_DEVSTAT_UTOPIA_EN_RESETVAL (0x00000000u)
/*----UTOPIA_EN Tokens----*/
#define CSL_DEV_DEVSTAT_UTOPIA_EN_DISABLE (0x00000000u)
#define CSL_DEV_DEVSTAT_UTOPIA_EN_ENABLE (0x00000001u)
#define CSL_DEV_DEVSTAT_LENDIAN_MASK (0x00000040u)
#define CSL_DEV_DEVSTAT_LENDIAN_SHIFT (0x00000006u)
#define CSL_DEV_DEVSTAT_LENDIAN_RESETVAL (0x00000001u)
/*----LENDIAN Tokens----*/
#define CSL_DEV_DEVSTAT_LENDIAN_BE (0x00000000u)
#define CSL_DEV_DEVSTAT_LENDIAN_LE (0x00000001u)
#define CSL_DEV_DEVSTAT_HPI_WIDTH_MASK (0x00000020u)
#define CSL_DEV_DEVSTAT_HPI_WIDTH_SHIFT (0x00000005u)
#define CSL_DEV_DEVSTAT_HPI_WIDTH_RESETVAL (0x00000000u)
/*----HPI_WIDTH Tokens----*/
#define CSL_DEV_DEVSTAT_HPI_WIDTH_16BIT (0x00000000u)
#define CSL_DEV_DEVSTAT_HPI_WIDTH_32BIT (0x00000001u)
#define CSL_DEV_DEVSTAT_AECLKINSEL_MASK (0x00000010u)
#define CSL_DEV_DEVSTAT_AECLKINSEL_SHIFT (0x00000004u)
#define CSL_DEV_DEVSTAT_AECLKINSEL_RESETVAL (0x00000000u)
/*----AECLKINSEL Tokens----*/
#define CSL_DEV_DEVSTAT_AECLKINSEL_AECLKIN (0x00000000u)
#define CSL_DEV_DEVSTAT_AECLKINSEL_SYSCLK4 (0x00000001u)
#define CSL_DEV_DEVSTAT_BOOTMODE_MASK (0x0000000Fu)
#define CSL_DEV_DEVSTAT_BOOTMODE_SHIFT (0x00000000u)
#define CSL_DEV_DEVSTAT_BOOTMODE_RESETVAL (0x00000000u)
/*----BOOTMODE Tokens----*/
#define CSL_DEV_DEVSTAT_BOOTMODE_NONE (0x00000000u)
#define CSL_DEV_DEVSTAT_BOOTMODE_HPI (0x00000001u)
#define CSL_DEV_DEVSTAT_BOOTMODE_EMIFA8BIT (0x00000004u)
#define CSL_DEV_DEVSTAT_BOOTMODE_MASTER_I2C (0x00000005u)
#define CSL_DEV_DEVSTAT_BOOTMODE_SLAVE_I2C (0x00000006u)
#define CSL_DEV_DEVSTAT_BOOTMODE_PCI (0x00000007u)
#define CSL_DEV_DEVSTAT_BOOTMODE_SRIO (0x00000008u)
#define CSL_DEV_DEVSTAT_RESETVAL (0x00000040u)
/* PRI_ALLOC */
#define CSL_DEV_PRI_ALLOC_SRIO_MASK (0x00000E00u)
#define CSL_DEV_PRI_ALLOC_SRIO_SHIFT (0x00000009u)
#define CSL_DEV_PRI_ALLOC_SRIO_RESETVAL (0x00000001u)
#define CSL_DEV_PRI_ALLOC_VLYNQ_MASK (0x000001C0u)
#define CSL_DEV_PRI_ALLOC_VLYNQ_SHIFT (0x00000006u)
#define CSL_DEV_PRI_ALLOC_VLYNQ_RESETVAL (0x00000004u)
#define CSL_DEV_PRI_ALLOC_HOST_MASK (0x00000038u)
#define CSL_DEV_PRI_ALLOC_HOST_SHIFT (0x00000003u)
#define CSL_DEV_PRI_ALLOC_HOST_RESETVAL (0x00000002u)
#define CSL_DEV_PRI_ALLOC_EMAC_MASK (0x00000007u)
#define CSL_DEV_PRI_ALLOC_EMAC_SHIFT (0x00000000u)
#define CSL_DEV_PRI_ALLOC_EMAC_RESETVAL (0x00000001u)
#define CSL_DEV_PRI_ALLOC_RESETVAL (0x00000311u)
/* JTAGID */
#define CSL_DEV_JTAGID_VARIANT_MASK (0xF0000000u)
#define CSL_DEV_JTAGID_VARIANT_SHIFT (0x0000001Cu)
#define CSL_DEV_JTAGID_VARIANT_RESETVAL (0x00000000u)
#define CSL_DEV_JTAGID_PARTNUMBER_MASK (0x0FFFF000u)
#define CSL_DEV_JTAGID_PARTNUMBER_SHIFT (0x0000000Cu)
#define CSL_DEV_JTAGID_PARTNUMBER_RESETVAL (0x0000008Au)
#define CSL_DEV_JTAGID_MANUFACTURER_MASK (0x00000FFEu)
#define CSL_DEV_JTAGID_MANUFACTURER_SHIFT (0x00000001u)
#define CSL_DEV_JTAGID_MANUFACTURER_RESETVAL (0x00000017u)
#define CSL_DEV_JTAGID_LSB_MASK (0x00000001u)
#define CSL_DEV_JTAGID_LSB_SHIFT (0x00000000u)
#define CSL_DEV_JTAGID_LSB_RESETVAL (0x00000001u)
#define CSL_DEV_JTAGID_RESETVAL (0x0008A02Fu)
/* PERLOCK */
#define CSL_DEV_PERLOCK_LOCKVAL_MASK (0xFFFFFFFFu)
#define CSL_DEV_PERLOCK_LOCKVAL_SHIFT (0x00000000u)
#define CSL_DEV_PERLOCK_LOCKVAL_RESETVAL (0xF0F0F0F0u)
/*----LOCKVAL Tokens----*/
#define CSL_DEV_PERLOCK_LOCKVAL_UNLOCK (0x0F0A0B00u)
#define CSL_DEV_PERLOCK_RESETVAL (0xF0F0F0F0u)
/* PERCFG0 */
#define CSL_DEV_PERCFG0_SRIOCTL_MASK (0xC0000000u)
#define CSL_DEV_PERCFG0_SRIOCTL_SHIFT (0x0000001Eu)
#define CSL_DEV_PERCFG0_SRIOCTL_RESETVAL (0x00000000u)
/*----SRIOCTL Tokens----*/
#define CSL_DEV_PERCFG0_SRIOCTL_DISABLE (0x00000000u)
#define CSL_DEV_PERCFG0_SRIOCTL_ENABLE (0x00000003u)
#define CSL_DEV_PERCFG0_RSA1CTL_MASK (0x10000000u)
#define CSL_DEV_PERCFG0_RSA1CTL_SHIFT (0x0000001Cu)
#define CSL_DEV_PERCFG0_RSA1CTL_RESETVAL (0x00000000u)
/*----RSA1CTL Tokens----*/
#define CSL_DEV_PERCFG0_RSA1CTL_DISABLE (0x00000000u)
#define CSL_DEV_PERCFG0_RSA1CTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_RSA0CTL_MASK (0x04000000u)
#define CSL_DEV_PERCFG0_RSA0CTL_SHIFT (0x0000001Au)
#define CSL_DEV_PERCFG0_RSA0CTL_RESETVAL (0x00000000u)
/*----RSA0CTL Tokens----*/
#define CSL_DEV_PERCFG0_RSA0CTL_DISABLE (0x00000000u)
#define CSL_DEV_PERCFG0_RSA0CTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_VLYNQCTL_MASK (0x01000000u)
#define CSL_DEV_PERCFG0_VLYNQCTL_SHIFT (0x00000018u)
#define CSL_DEV_PERCFG0_VLYNQCTL_RESETVAL (0x00000000u)
/*----VLYNQCTL Tokens----*/
#define CSL_DEV_PERCFG0_VLYNQCTL_DISABLE (0x00000000u)
#define CSL_DEV_PERCFG0_VLYNQCTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_UTOPIACTL_MASK (0x00400000u)
#define CSL_DEV_PERCFG0_UTOPIACTL_SHIFT (0x00000016u)
#define CSL_DEV_PERCFG0_UTOPIACTL_RESETVAL (0x00000000u)
/*----UTOPIACTL Tokens----*/
#define CSL_DEV_PERCFG0_UTOPIACTL_DISABLE (0x00000000u)
#define CSL_DEV_PERCFG0_UTOPIACTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_PCICTL_MASK (0x00100000u)
#define CSL_DEV_PERCFG0_PCICTL_SHIFT (0x00000014u)
#define CSL_DEV_PERCFG0_PCICTL_RESETVAL (0x00000000u)
/*----PCICTL Tokens----*/
#define CSL_DEV_PERCFG0_PCICTL_DISABLE (0x00000000u)
#define CSL_DEV_PERCFG0_PCICTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_HPICTL_MASK (0x00040000u)
#define CSL_DEV_PERCFG0_HPICTL_SHIFT (0x00000012u)
#define CSL_DEV_PERCFG0_HPICTL_RESETVAL (0x00000000u)
/*----HPICTL Tokens----*/
#define CSL_DEV_PERCFG0_HPICTL_DISABLE (0x00000000u)
#define CSL_DEV_PERCFG0_HPICTL_ENABLE (0x00000001u)
#define CSL_DEV_PERCFG0_MCBSP1CTL_MASK (0x00010000u)
#define CSL_DEV_PERCFG0_MCBSP1CTL_SHIFT (0x00000010u)
#define CSL_DEV_PERCFG0_MCBSP1CTL_RESETVAL (0x00000000u)
/*----MCBSP1CTL Tokens----*/
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