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📄 koe_tmp.mdl

📁 一个WCDMA接收机的matlab程序
💻 MDL
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      ForegroundColor	      "green"      NamePlacement	      "alternate"      ShowName		      off      SourceBlock	      "utra_lib/test functions/hard decission"      SourceType	      "Unknown"      mode		      "off"      N			      "16*N"      thres		      "0"      nFrames		      "1"    }    Block {      BlockType		      Reference      Name		      "inter_interleaving"      Ports		      [1, 1, 0, 0, 0]      Position		      [20, 135, 120, 195]      Orientation	      "down"      ForegroundColor	      "green"      ShowName		      off      SourceBlock	      "utra_lib/DL/dl_TX_modulation/inter_interleaving"      SourceType	      "Unknown"      bits_in_frame	      "N*16"      nFrames		      "1"      cols		      "1"    }    Block {      BlockType		      Reference      Name		      "inter_interleaving1"      Ports		      [2, 2, 0, 0, 0]      Position		      [680, 468, 815, 617]      Orientation	      "left"      ForegroundColor	      "green"      ShowName		      off      SourceBlock	      "utra_lib/DL/dl_RX_demodulation/inter_interleavi""ng"      SourceType	      "Unknown"      bits_in_frame	      "N*16"      rows		      "1"      nFrames		      "1"    }    Block {      BlockType		      Reference      Name		      "intra_de_interleaving"      Ports		      [2, 2, 0, 0, 0]      Position		      [850, 469, 980, 616]      Orientation	      "left"      ForegroundColor	      "green"      ShowName		      off      SourceBlock	      "utra_lib/DL/dl_RX_demodulation/intra_de_interle""aving"      SourceType	      "Unknown"      nDeIntra		      "16*N"      nFrames		      "1"      Intra_int_flag	      "0"    }    Block {      BlockType		      Reference      Name		      "intra_interleaving"      Ports		      [1, 1, 0, 0, 0]      Position		      [100, 281, 180, 349]      ForegroundColor	      "yellow"      ShowName		      off      SourceBlock	      "utra_lib/DL/dl_TX_modulation/intra_interleaving""1"      SourceType	      "Unknown"      bits_in_frame	      "N*16"      nFrames		      "1"      nSlot		      "16"      Intra_int_flag	      "0"    }    Block {      BlockType		      Reference      Name		      "modulation"      Ports		      [1, 2, 0, 0, 0]      Position		      [210, 226, 300, 399]      ForegroundColor	      "red"      ShowName		      off      SourceBlock	      "utra_lib/DL/dl_TX_modulation/modulation"      SourceType	      "Unknown"      Ndisc		      "N"      C			      "C"      nSlot		      "16"    }    Block {      BlockType		      Reference      Name		      "rake"      Ports		      [5, 4, 0, 0, 0]      Position		      [675, 232, 830, 388]      ForegroundColor	      "red"      ShowName		      off      FontName		      "helvetica"      FontSize		      12      FontWeight	      "bold"      SourceBlock	      "utra_lib/DL/dl_RX_demodulation/rake"      SourceType	      "Unknown"      N_rake		      "N*length(C)/2"      nSlot		      "16"      nPilot		      "0"      th		      "0.1"      nFin		      "1"      SF		      "length(C)"      C			      "C"    }    Line {      SrcBlock		      "hard "      SrcPort		      1      DstBlock		      "Direct ber calculation"      DstPort		      2    }    Line {      SrcBlock		      "channel3"      SrcPort		      1      Points		      [25, 0]      Branch {	DstBlock		"rake"	DstPort			1      }      Branch {	DstBlock		"hard "	DstPort			1      }    }    Line {      SrcBlock		      "Direct ber calculation"      SrcPort		      1      Points		      [0, -20]      Branch {	DstBlock		"Display36"	DstPort			1      }      Branch {	DstBlock		"To Workspace14"	DstPort			1      }    }    Line {      SrcBlock		      "rake"      SrcPort		      1      DstBlock		      "demodulation"      DstPort		      1    }    Line {      SrcBlock		      "data source 01 ..10"      SrcPort		      1      Points		      [0, 15]      Branch {	DstBlock		"To Workspace4"	DstPort			1      }      Branch {	DstBlock		"inter_interleaving"	DstPort			1      }    }    Line {      SrcBlock		      "inter_interleaving"      SrcPort		      1      Points		      [0, 55]      Branch {	Points			[0, 255; 200, 0]	DstBlock		"Delayed ber calculation"	DstPort			1      }      Branch {	Points			[0, 60]	DstBlock		"intra_interleaving"	DstPort			1      }    }    Line {      SrcBlock		      "channel3"      SrcPort		      2      DstBlock		      "Channel estimator1"      DstPort		      1    }    Line {      SrcBlock		      "channel3"      SrcPort		      3      DstBlock		      "Channel estimator1"      DstPort		      2    }    Line {      SrcBlock		      "Channel estimator1"      SrcPort		      1      Points		      [20, 0]      Branch {	Labels			[1, 0]	Points			[0, -165]	DstBlock		"To Workspace8"	DstPort			1      }      Branch {	DstBlock		"rake"	DstPort			2      }    }    Line {      SrcBlock		      "Channel estimator1"      SrcPort		      2      DstBlock		      "rake"      DstPort		      3    }    Line {      SrcBlock		      "Channel estimator1"      SrcPort		      3      DstBlock		      "rake"      DstPort		      4    }    Line {      SrcBlock		      "modulation"      SrcPort		      1      Points		      [10, 0]      Branch {	DstBlock		"channel3"	DstPort			1      }      Branch {	Points			[0, -55; 120, 0]	DstBlock		"Direct ber calculation"	DstPort			1      }    }    Line {      SrcBlock		      "rake"      SrcPort		      2      DstBlock		      "demodulation"      DstPort		      2    }    Line {      SrcBlock		      "rake"      SrcPort		      4      DstBlock		      "demodulation"      DstPort		      4    }    Line {      SrcBlock		      "rake"      SrcPort		      3      DstBlock		      "demodulation"      DstPort		      3    }    Line {      Labels		      [1, 0]      SrcBlock		      "modulation"      SrcPort		      2      DstBlock		      "channel3"      DstPort		      2    }    Line {      SrcBlock		      "channel3"      SrcPort		      4      DstBlock		      "rake"      DstPort		      5    }    Line {      SrcBlock		      "intra_interleaving"      SrcPort		      1      DstBlock		      "modulation"      DstPort		      1    }    Line {      SrcBlock		      "demodulation"      SrcPort		      2      Points		      [15, 0]      Branch {	DstBlock		"To Workspace16"	DstPort			1      }      Branch {	Points			[0, 230]	DstBlock		"intra_de_interleaving"	DstPort			2      }    }    Line {      SrcBlock		      "Delayed ber calculation"      SrcPort		      1      Points		      [0, 25]      Branch {	DstBlock		"Display35"	DstPort			1      }      Branch {	DstBlock		"To Workspace12"	DstPort			1      }    }    Line {      SrcBlock		      "intra_de_interleaving"      SrcPort		      1      DstBlock		      "inter_interleaving1"      DstPort		      1    }    Line {      SrcBlock		      "intra_de_interleaving"      SrcPort		      2      DstBlock		      "inter_interleaving1"      DstPort		      2    }    Line {      SrcBlock		      "inter_interleaving1"      SrcPort		      2      DstBlock		      "Display37"      DstPort		      1    }    Line {      SrcBlock		      "hard 1"      SrcPort		      1      Points		      [-75, 0]      DstBlock		      "Delayed ber calculation"      DstPort		      2    }    Line {      SrcBlock		      "inter_interleaving1"      SrcPort		      1      Points		      [-100, 0]      Branch {	DstBlock		"hard 1"	DstPort			1      }      Branch {	Points			[30, 0; 0, -50]	DstBlock		"To Workspace7"	DstPort			1      }    }    Line {      SrcBlock		      "demodulation"      SrcPort		      1      Points		      [40, 0; 0, 235]      DstBlock		      "intra_de_interleaving"      DstPort		      1    }    Annotation {      Position		      [838, 75]      Text		      "TESTING MODEL FOR\n\ninterleavers\nmodulation\n""channel \nrake receiver\ndemodulation\ndeinterleavers"      FontName		      "helvetica"      FontSize		      14      FontWeight	      "bold"    }    Annotation {      Position		      [1028, 50]      Text		      "Defined in opening this model:\n\nN = 32\nC  = ""[ 1 1 -1 -1 ]\n"      FontName		      "helvetica"      FontSize		      12      FontWeight	      "bold"    }  }}

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