📄 vend_cbw.lst
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C51 COMPILER V7.50 VEND_CBW 10/12/2007 17:05:45 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE VEND_CBW
OBJECT MODULE PLACED IN vend_cbw.OBJ
COMPILER INVOKED BY: d:\Keil\C51\BIN\C51.EXE vend_cbw.c OBJECTADVANCED OPTIMIZE(11,SIZE) REGFILE(.\nand_fw2k.ORC) BROWSE
- ORDER INCDIR(c:\cypress\usb\target\inc) DEFINE(NAND_2K) DEBUG
line level source
1 //-----------------------------------------------------------------------------
2 // Copyright (c) 2005 Cypress Semiconductor, Inc. All rights reserved
3 //-----------------------------------------------------------------------------
4
5 //--------------------------------------------------------------------------
6
7 #include "globals.h"
8
9 #define NX2LP_CMD 0xC8 // NX2LP Manufacturing/Validation command support
10 #define CBW_NAND_READ_PAGE 0 // <bank><page><len> Read NAND Page (only 528 or 2K+64)
11 #define CBW_NAND_WRITE_PAGE 1 // <bank><page><len> Write NAND page (only 528 or 2K+64)
12 #define CBW_NAND_ERASE_BLK 2 // <bank><block> Erase Block (single block)
13 #define CBW_NAND_READ_REDUNDANT 3 // <bank><page> Read Redundant <block number>
14 #define CBW_NAND_READ_FLASH_ID 4 // <bank><len=7> Read Flash ID: return 4-byte ID, 2-status, 1-nand
-type
15 #define CBW_NAND_ERASE_ALL 5 // <bank><skip> Erase All with <skip bad block=1>
16 #define CBW_NAND_SET_ERR 6 // Simulate NAND error on NAND Read Status
17 #define CBW_NAND_GEN_CMD 7 // TBD (need design)
18 #define CBW_8051_LUT_DUMP 8 // <len>
19 #define CBW_8051_MEM_READ 9 // <address><len> 8051 memory read
20 #define CBW_8051_MEM_WRITE 0xa // <address><len> 8051 memory write
21 #define CBW_8051_RENUM 0xb // re-enumeration
22 #define CBW_READ_UNIQUE_ID 0xc // Read NAND unique ID
23
24 //-----------------------------------------------------------------------------
25 // Configure FIFO6 to read data from NAND
26 //-----------------------------------------------------------------------------
27 void Fifo6In() { P_FIFORESET=6, P_EP6CFG=EP6CFG_IN_DEFAULT; }
28
29 //-----------------------------------------------------------------------------
30 // Send Command to NAND chip
31 // cmd = NAND Command
32 //-----------------------------------------------------------------------------
33 void NandSendCmd(BYTE cmd)
34 {
35 1 NAND_CLE=1, P_XGPIFSGLDATLX=cmd, NAND_CLE=0;
36 1 }
37
38 //-----------------------------------------------------------------------------
39 // General read data from NAND using GPIF wave form 0
40 //-----------------------------------------------------------------------------
41 void NandRead(BYTE ep, WORD len)
42 {
43 1 nand_ready3();
44 1 FifoRd(ep, len);
45 1 }
46
47 //-----------------------------------------------------------------------------
48 // Get NAND Type
49 // EP6FIFOBUF contains 4-bytes ID, 2-byte status, 1-byte=bNand2k
50 //-----------------------------------------------------------------------------
51 void GetNandType()
52 {
53 1 Fifo6In(); // need this for reading data, see waveform
C51 COMPILER V7.50 VEND_CBW 10/12/2007 17:05:45 PAGE 2
54 1 NandSendCmd(cNAND_READ_ID);
55 1 NAND_ALE=1, P_XGPIFSGLDATLX=0, NAND_ALE=0;
56 1 NandRead(cEP6,4-1); // read NAND ID: 4 bytes
57 1 NandSendCmd(cNAND_READ_STATUS);
58 1 NandRead(cEP6,2-1); // read status 2 bytes
59 1
60 1 // 512/2K NAND Auto detect should be done here
61 1 // Use NAND_2K as sharing 2K/512 FW code
62 1 #ifdef NAND_2K
63 1 bNand2k = 1; // force this bit = 2K NAND
64 1 #else
bNand2k = 0; // force this bit = 512 NAND
#endif
67 1 EP6FIFOBUF[6]= bNand2k; // return NAND type
68 1 }
69
70 //-----------------------------------------------------------------------------
71 // NAND Set Address: Take 2.2 us for 512P NAND
72 // msk = 0-3, read page 1-4
73 // msk = 4, read offset 0x830 = redundant
74 // return none
75 // global: bit bNand2k = 1 = 2KP NAND, else 512P NAND
76 // gPhyAdd: set this before call this subroutine
77 //-----------------------------------------------------------------------------
78 // for 2K NAND sub-page address: 0=0x000 1=0x210, 2=0x420, 3=0x630, 4=0x830
79 const char code nadd0[5]={0, 0x10, 0x20, 0x30, 0x30};
80 const char code nadd1[5]={0, 0x02, 0x04, 0x06, 0x08};
81 void NandSetAdd(BYTE cmd, BYTE msk)
82 {
83 1 nand_ready3();
84 1 NAND_CLE=1,P_XGPIFSGLDATLX=cmd, NAND_CLE=0;
85 1 NAND_ALE = 1;
86 1 if (bNand2k)
87 1 {
88 2 P_XGPIFSGLDATLX = nadd0[msk];
89 2 P_XGPIFSGLDATLX = nadd1[msk];
90 2 }
91 1 else
92 1 P_XGPIFSGLDATLX = 0;
93 1 P_XGPIFSGLDATLX = ((BYTE *)&gPhyAdd)[3];
94 1 P_XGPIFSGLDATLX = ((BYTE *)&gPhyAdd)[2];
95 1 P_XGPIFSGLDATLX = ((BYTE *)&gPhyAdd)[1];
96 1 NAND_ALE = 0;
97 1 if (bNand2k && cmd==cNAND_READ_DATA) NAND_CLE=1, P_XGPIFSGLDATLX=cNAND_READ_START, NAND_CLE=0;
98 1 }
99
100 //-----------------------------------------------------------------------------
101 // Reading NAND Configuration page
102 // The reading always support ECC correction
103 //-----------------------------------------------------------------------------
104 bit nReadCfgPage()
105 {
106 1 Fifo6In();
107 1 P_ECCRESET=0;
108 1 NandSetAdd(cNAND_READ_DATA, 0);
109 1 NandRead(cEP6, cNAND_PSIZE); // always read 512+16 bytes
110 1 ECCSetup(EP6FIFOBUF+512+cCFG_ECC_OFF);
111 1 gPhyAdd++; // next page
112 1 return CorrectData(); // always correct data
113 1 }
114
115 //-----------------------------------------------------------------------------
C51 COMPILER V7.50 VEND_CBW 10/12/2007 17:05:45 PAGE 3
116 // nCopyBlock:
117 // Correct Bad ECC Block for both 2K NAND and 512 NAND
118 // Mark the block bad with 0xF0 if there is more than 2-bit ECC error
119 // bSofErr will control the
120 /// Mark the block bad with multiple repeat 1-bit ECC errors
121 //-----------------------------------------------------------------------------
122 void nCopyBlock()
123 {
124 1
125 1 #ifdef NAND_2K // 2K FW code
126 1 BYTE xdata cnt;
127 1 bit bECC_Retry;
128 1 xbyte *p;
129 1 WORD xdata pa0;
130 1
131 1 #ifdef USE_2NAND
if (gBank==0) CE0_ON(); else CE1_ON();
#else
134 1 IOD = gEnableBanks;
135 1 #endif
136 1 p = (xbyte*)&gLog2Phy[gSrc];
137 1 bECC_Retry = (*p & MSB(cBLK_ECC));
138 1 *p |= MSB(cBLK_ECC); // set ECC bit
139 1
140 1 pa0 = gCurZone << cMaxBlock2N; // compute Zone
141 1 gSrcAdd = ((DWORD)(pa0 | gSrc) << c2KPageSize2N);
142 1 gSrcBlk0 = ((BYTE *)&gSrcAdd)[3];
143 1 nGetFreeBlk(); // return gFreeBlk
144 1 gPhyAdd = ((DWORD)(pa0 | gFreeBlk) << c2KPageSize2N);
145 1
146 1 b2BitErr = 0;
147 1 nCopyPages(0, 0); // copy and correct ECC data
148 1 bNeedErase=1;
149 1 if (b2BitErr || (bECC_Retry && !bSoftErr))
150 1 {
151 2 if (b2BitErr) // more than 2 bit need to erase
152 2 {
153 3 xPhyAdd -= c2KPageSize2N; // need to erase good block
154 3 nand_blk_erase(gPhyAdd);
155 3 }
156 2 // mask the src block bad
157 2 ((BYTE *)&gPhyAdd)[3] = gSrcBlk0;
158 2 ((BYTE *)&gPhyAdd)[2] = ((BYTE *)&gSrcAdd)[2];
159 2 ((BYTE *)&gPhyAdd)[1] = ((BYTE *)&gSrcAdd)[1];
160 2
161 2 NandSetAdd(cNAND_WRITE_DATA, 3);
162 2 for (cnt=0; cnt<(528/4); cnt++) // mask this block bad
163 2 {
164 3 P_XGPIFSGLDATLX = 0xf0; _nop_();
165 3 P_XGPIFSGLDATLX = 0xf0; _nop_();
166 3 P_XGPIFSGLDATLX = 0xf0; _nop_();
167 3 P_XGPIFSGLDATLX = 0xf0;
168 3 }
169 2 NandSendCmd(cNAND_PROGRAM_PAGE); // program only one page
170 2 gCurZone = 0xff; // refresh the LUT
171 2 }
172 1 else
173 1 {
174 2 *p &= MSB(~cBLK_USE); // set this block free
175 2 *(xbyte*)&gLog2Phy[gFreeBlk] |= MSB(cBLK_USE); // Set this block is used
176 2 *pDst = (*pDst & cBLK_uMSK) | gFreeBlk; // update Logical address
177 2 nEraseBlock(); // erase block
C51 COMPILER V7.50 VEND_CBW 10/12/2007 17:05:45 PAGE 4
178 2 }
179 1
180 1 #else // 512 FW code
BYTE cnt=32;
bit bECC_Retry;
xbyte *p;
WORD pa0;
if (bInterLeave) cnt=64; // (32 page per NAND)*2
#ifdef USE_2NAND
CE0_ON(), CE1_ON();
#else
IOD = gEnableBanks;
#endif
p = (xbyte*)&gLog2Phy[gSrc];
bECC_Retry = (*p & MSB(cBLK_ECC));
*p |= MSB(cBLK_ECC); // set ECC bit
pa0 = gCurZone << cMaxBlock2N; // compute Zone
gSrcAdd = ((DWORD)(pa0 | gSrc) << c512PageSize2N);
gSrcBlk0 = ((BYTE *)&gSrcAdd)[3];
nGetFreeBlk(); // return gFreeBlk
gPhyAdd = ((DWORD)(pa0 | gFreeBlk) << c512PageSize2N);
b2BitErr = 0;
nCopyPages(cnt, 0); // copy and correct ECC data
bNeedErase=1;
if (b2BitErr || (bECC_Retry && !bSoftErr))
{
#ifdef USE_2NAND
CE0_ON(), CE1_ON();
#else
IOD = gEnableBanks;
#endif
if (b2BitErr) // more than 2 bit need to erase
{
xPhyAdd -= c512PageSize2N; // need to erase good block
nand_blk_erase(gPhyAdd);
}
// mask the src block bad
((BYTE *)&gPhyAdd)[3] = gSrcBlk0;
((BYTE *)&gPhyAdd)[2] = ((BYTE *)&gSrcAdd)[2];
((BYTE *)&gPhyAdd)[1] = ((BYTE *)&gSrcAdd)[1];
NandSetAdd(cNAND_WRITE_DATA, 3);
for (cnt=0; cnt<(528/4); cnt++) // mask this block bad
{
P_XGPIFSGLDATLX = 0xf0; _nop_();
P_XGPIFSGLDATLX = 0xf0; _nop_();
P_XGPIFSGLDATLX = 0xf0; _nop_();
P_XGPIFSGLDATLX = 0xf0;
}
NandSendCmd(cNAND_PROGRAM_PAGE); // program only one page
gCurZone = 0xff; // refresh the LUT
}
else
{
*p &= MSB(~cBLK_USE); // set this block free
*(xbyte*)&gLog2Phy[gFreeBlk] |= MSB(cBLK_USE); // Set this block is used
*pDst = (*pDst & cBLK_uMSK) | gFreeBlk; // update Logical address
C51 COMPILER V7.50 VEND_CBW 10/12/2007 17:05:45 PAGE 5
nEraseBlock(); // erase block
}
#endif
243 1 DISABLE_NAND();
244 1 }
245
246 //-----------------------------------------------------------------------------
247 // Get NAND configuration data
248 // This code follow the Boot-Loader code to get configuration data and
249 // Vendor Strings
250 // This code supports both 2K and 512 NAND types
251 //-----------------------------------------------------------------------------
252 void GetNandCfg()
253 {
254 1 BYTE xdata n, ID, ntype, bank;
255 1 bit nand=0;
256 1
257 1 gZones = cMaxZone; // 512: default = 8 zone
258 1 #ifdef USE_2NAND
CE0_ON();
#else
261 1 IOD = 0xFE; // start from Bank0
262 1 #endif
263 1 GetNandType(); // Get ID & Status byte
264 1 GetNandType(); // Get ID & Status byte
265 1 ID = EP6FIFOBUF[0]; // get NAND ID
266 1 ntype = EP6FIFOBUF[1]; // get NAND ID
267 1 for (bank=0; bank<2 && nand==0; bank++)
268 1 {
269 2 for (n=0; n<cMaxBlkChk; n++)
270 2 {
271 3 if (bNand2k==0) gPhyAdd = n << 5; else gPhyAdd = n << 6;
272 3 if ( (nReadCfgPage()==cOK) && // make sure no ECC error
273 3 (CheckSignature()==cOK) ) // check signature and NAND configuration
274 3 {
275 4 nand = 1; // CFG found break out loop
276 4 break;
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