📄 reset.lst
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+1 192 ; EP4GPIFTCH XDATA 0xE6D8 ; EP4 GPIF Transaction Count High
+1 193 ; EP4GPIFTCL XDATA 0xE6D9 ; EP4 GPIF Transactionr Count Low
E6DA +1 194 EP4GPIFFLGSEL XDATA 0xE6DA ; EP4 GPIF Flag select
E6DB +1 195 EP4GPIFPFSTOP XDATA 0xE6DB ; Stop GPIF EP4 transaction on prog. flag
E6DC +1 196 EP4GPIFTRIG XDATA 0xE6DC ; EP4 FIFO Trigger
+1 197 ; EP6GPIFTCH XDATA 0xE6E0 ; EP6 GPIF Transaction Count High
+1 198 ; EP6GPIFTCL XDATA 0xE6E1 ; EP6 GPIF Transaction Count Low
E6E2 +1 199 EP6GPIFFLGSEL XDATA 0xE6E2 ; EP6 GPIF Flag select
E6E3 +1 200 EP6GPIFPFSTOP XDATA 0xE6E3 ; Stop GPIF EP6 transaction on prog. flag
E6E4 +1 201 EP6GPIFTRIG XDATA 0xE6E4 ; EP6 FIFO Trigger
+1 202 ; EP8GPIFTCH XDATA 0xE6E8 ; EP8 GPIF Transaction Count High
+1 203 ; EP8GPIFTCL XDATA 0xE6E9 ; EP8GPIF Transaction Count Low
E6EA +1 204 EP8GPIFFLGSEL XDATA 0xE6EA ; EP8 GPIF Flag select
E6EB +1 205 EP8GPIFPFSTOP XDATA 0xE6EB ; Stop GPIF EP8 transaction on prog. flag
E6EC +1 206 EP8GPIFTRIG XDATA 0xE6EC ; EP8 FIFO Trigger
E6F0 +1 207 XGPIFSGLDATH XDATA 0xE6F0 ; GPIF Data H (16-bit mode only)
E6F1 +1 208 XGPIFSGLDATLX XDATA 0xE6F1 ; Read/Write GPIF Data L & trigger transac
E6F2 +1 209 XGPIFSGLDATLNOX XDATA 0xE6F2 ; Read GPIF Data L, no transac trigger
E6F3 +1 210 GPIFREADYCFG XDATA 0xE6F3 ; Internal RDY,Sync/Async, RDY5CFG
E6F4 +1 211 GPIFREADYSTAT XDATA 0xE6F4 ; RDY pin states
E6F5 +1 212 GPIFABORT XDATA 0xE6F5 ; Abort GPIF cycles
+1 213
+1 214 ; UDMA
+1 215
E6C6 +1 216 FLOWSTATE XDATA 0xE6C6 ; Defines GPIF flow state
E6C7 +1 217 FLOWLOGIC XDATA 0xE6C7 ; Defines flow/hold decision criteria
E6C8 +1 218 FLOWEQ0CTL XDATA 0xE6C8 ; CTL states during active flow state
E6C9 +1 219 FLOWEQ1CTL XDATA 0xE6C9 ; CTL states during hold flow state
E6CB +1 220 FLOWSTB XDATA 0xE6CB ; CTL/RDY Signal to use as master data strobe
E6CC +1 221 FLOWEDGE XDATA 0xE6CC ; Defines active master strobe edge
E6CD +1 222 FLOWSTBHPERIOD XDATA 0xE6CD ; Half Period of output master strobe
E60C +1 223 GPIFHOLDAMOUNT XDATA 0xE60C ; Data delay shift
E67D +1 224 UDMACRCH XDATA 0xE67D ; CRC Upper byte
E67E +1 225 UDMACRCL XDATA 0xE67E ; CRC Lower byte
E67F +1 226 UDMACRCQUAL XDATA 0xE67F ; UDMA In only, host terminated use only
+1 227
+1 228
+1 229 ; Debug/Test
+1 230
E6F8 +1 231 DBUG XDATA 0xE6F8 ; Debug
E6F9 +1 232 TESTCFG XDATA 0xE6F9 ; Test configuration
E6FA +1 233 USBTEST XDATA 0xE6FA ; USB Test Modes
E6FB +1 234 CT1 XDATA 0xE6FB ; Chirp Test--Override
E6FC +1 235 CT2 XDATA 0xE6FC ; Chirp Test--FSM
E6FD +1 236 CT3 XDATA 0xE6FD ; Chirp Test--Control Signals
E6FE +1 237 CT4 XDATA 0xE6FE ; Chirp Test--Inputs
+1 238
+1 239 ; Endpoint Buffers
+1 240
E740 +1 241 EP0BUF XDATA 0xE740 ; EP0 IN-OUT buffer
E780 +1 242 EP10UTBUF XDATA 0xE780 ; EP1-OUT buffer
E7C0 +1 243 EP1INBUF XDATA 0xE7C0 ; EP1-IN buffer
F000 +1 244 EP2FIFOBUF XDATA 0xF000 ; 512/1024-byte EP2 buffer (IN or OUT)
F400 +1 245 EP4FIFOBUF XDATA 0xF400 ; 512 byte EP4 buffer (IN or OUT)
F800 +1 246 EP6FIFOBUF XDATA 0xF800 ; 512/1024-byte EP6 buffer (IN or OUT)
FC00 +1 247 EP8FIFOBUF XDATA 0xFC00 ; 512 byte EP8 buffer (IN or OUT)
+1 248
+1 249 ;/*-----------------------------------------------------------------------------
+1 250 ; Special Function Registers (SFRs)
+1 251 ; The byte registers and bits defined in the following list are based
+1 252 ; on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
+1 253 ; If you modify the register definitions below, please regenerate the file
+1 254 ; "ezregs.inc" which includes the same basic information for assembly inclusion.
+1 255 ;-----------------------------------------------------------------------------*/
AX51 MACRO ASSEMBLER RESET 10/12/07 16:09:52 PAGE 5
+1 256
0080 +1 257 IOA DATA 080H
0081 +1 258 SP DATA 081H
0082 +1 259 DPL DATA 082H
0083 +1 260 DPH DATA 083H
0084 +1 261 DPL1 DATA 084H
0085 +1 262 DPH1 DATA 085H
0086 +1 263 DPS DATA 086H
+1 264 ; DPS
0080.6 +1 265 SEL BIT 086H+0H
0087 +1 266 PCON DATA 087H
+1 267 ; PCON
+1 268 ;IDLE BIT 087H+0H
+1 269 ;STOP BIT 087H+1H
+1 270 ;GF0 BIT 087H+2H
+1 271 ;GF1 BIT 087H+3H
+1 272 ;SMOD0 BIT 087H+7H
0088 +1 273 TCON DATA 088H
+1 274 ; TCON
0088.0 +1 275 IT0 BIT 088H+0H
0088.1 +1 276 IE0 BIT 088H+1H
0088.2 +1 277 IT1 BIT 088H+2H
0088.3 +1 278 IE1 BIT 088H+3H
0088.4 +1 279 TR0 BIT 088H+4H
0088.5 +1 280 TF0 BIT 088H+5H
0088.6 +1 281 TR1 BIT 088H+6H
0088.7 +1 282 TF1 BIT 088H+7H
0089 +1 283 TMOD DATA 089H
+1 284 ; TMOD
+1 285 ;M00 BIT 089H+0H
+1 286 ;M10 BIT 089H+1H
+1 287 ;CT0 BIT 089H+2H
+1 288 ;GATE0 BIT 089H+3H
+1 289 ;M01 BIT 089H+4H
+1 290 ;M11 BIT 089H+5H
+1 291 ;CT1 BIT 089H+6H
+1 292 ;GATE1 BIT 089H+7H
008A +1 293 TL0 DATA 08AH
008B +1 294 TL1 DATA 08BH
008C +1 295 TH0 DATA 08CH
008D +1 296 TH1 DATA 08DH
008E +1 297 CKCON DATA 08EH
+1 298 ; CKCON
+1 299 ;MD0 BIT 089H+0H
+1 300 ;MD1 BIT 089H+1H
+1 301 ;MD2 BIT 089H+2H
+1 302 ;T0M BIT 089H+3H
+1 303 ;T1M BIT 089H+4H
+1 304 ;T2M BIT 089H+5H
+1 305 ;SPC_FNC DATA 08FH ; Was WRS in Reg320
+1 306 ; CKCON
+1 307 ;WRS BIT 08FH+0H
0090 +1 308 IOB DATA 090H
0091 +1 309 EXIF DATA 091H ; EXIF Bit Values differ from Reg320
+1 310 ; EXIF
+1 311 ;USBINT BIT 091H+4H
+1 312 ;I2CINT BIT 091H+5H
+1 313 ;IE4 BIT 091H+6H
+1 314 ;IE5 BIT 091H+7H
0092 +1 315 MPAGE DATA 092H
0098 +1 316 SCON0 DATA 098H
+1 317 ; SCON0
0098.0 +1 318 RI BIT 098H+0H
0098.1 +1 319 TI BIT 098H+1H
0098.2 +1 320 RB8 BIT 098H+2H
0098.3 +1 321 TB8 BIT 098H+3H
AX51 MACRO ASSEMBLER RESET 10/12/07 16:09:52 PAGE 6
0098.4 +1 322 REN BIT 098H+4H
0098.5 +1 323 SM2 BIT 098H+5H
0098.6 +1 324 SM1 BIT 098H+6H
0098.7 +1 325 SM0 BIT 098H+7H
0099 +1 326 SBUF0 DATA 099H
+1 327
009A +1 328 APTR1H DATA 09AH ; old name
009B +1 329 APTR1L DATA 09BH ; old name
009A +1 330 AUTOPTR1H DATA 09AH
009B +1 331 AUTOPTR1L DATA 09BH
009D +1 332 AUTOPTRH2 DATA 09DH
009E +1 333 AUTOPTRL2 DATA 09EH
00A0 +1 334 IOC DATA 0A0H
00A1 +1 335 INT2CLR DATA 0A1H
00A2 +1 336 INT4CLR DATA 0A2H
+1 337
00A8 +1 338 IE DATA 0A8H
+1 339 ; IE
00A8.0 +1 340 EX0 BIT 0A8H+0H
00A8.1 +1 341 ET0 BIT 0A8H+1H
00A8.2 +1 342 EX1 BIT 0A8H+2H
00A8.3 +1 343 ET1 BIT 0A8H+3H
00A8.4 +1 344 ES0 BIT 0A8H+4H
00A8.5 +1 345 ET2 BIT 0A8H+5H
00A8.6 +1 346 ES1 BIT 0A8H+6H
00A8.7 +1 347 EA BIT 0A8H+7H
+1 348
00AA +1 349 EP2468STAT DATA 0AAH
+1 350 ; EP2468STAT
+1 351 ;EP2E BIT 0AAH+0H
+1 352 ;EP2F BIT 0AAH+1H
+1 353 ;EP4E BIT 0AAH+2H
+1 354 ;EP4F BIT 0AAH+3H
+1 355 ;EP6E BIT 0AAH+4H
+1 356 ;EP6F BIT 0AAH+5H
+1 357 ;EP8E BIT 0AAH+6H
+1 358 ;EP8F BIT 0AAH+7H
+1 359
00AB +1 360 EP24FIFOFLGS DATA 0ABH
00AC +1 361 EP68FIFOFLGS DATA 0ACH
00AF +1 362 AUTOPTRSETUP DATA 0AFH
+1 363 ; AUTOPTRSETUP
+1 364 ;EXTACC BIT 0AFH+0H
+1 365 ;APTR1FZ BIT 0AFH+1H
+1 366 ;APTR2FZ BIT 0AFH+2H
+1 367
00B0 +1 368 IOD DATA 0B0H
00B1 +1 369 IOE DATA 0B1H
00B2 +1 370 OEA DATA 0B2H
00B3 +1 371 OEB DATA 0B3H
00B4 +1 372 OEC DATA 0B4H
00B5 +1 373 OED DATA 0B5H
00B6 +1 374 OEE DATA 0B6H
+1 375
00B8 +1 376 IP DATA 0B8H
+1 377 ; IP
00B8.0 +1 378 PX0 BIT 0B8H+0H
00B8.1 +1 379 PT0 BIT 0B8H+1H
00B8.2 +1 380 PX1 BIT 0B8H+2H
00B8.3 +1 381 PT1 BIT 0B8H+3H
00B8.4 +1 382 PS0 BIT 0B8H+4H
00B8.5 +1 383 PT2 BIT 0B8H+5H
00B8.6 +1 384 PS1 BIT 0B8H+6H
+1 385
00BA +1 386 EP01STAT DATA 0BAH
00BB +1 387 GPIFTRIG DATA 0BBH
AX51 MACRO ASSEMBLER RESET 10/12/07 16:09:52 PAGE 7
+1 388
00BD +1 389 GPIFSGLDATH DATA 0BDH
00BE +1 390 GPIFSGLDATLX DATA 0BEH
00BF +1 391 GPIFSGLDATLNOX DATA 0BFH
+1 392
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