📄 reset.lst
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AX51 MACRO ASSEMBLER RESET 10/12/07 16:09:52 PAGE 1
MACRO ASSEMBLER AX51 V2.14
OBJECT MODULE PLACED IN reset.OBJ
ASSEMBLER INVOKED BY: d:\Keil\C51\BIN\AX51.EXE reset.a51 INCDIR(c:\cypress\usb\target\inc) SET(SMALL) DEBUG EP
LOC OBJ LINE SOURCE
1 ;-----------------------------------------------------------------------------
2 ; File: reset.a51
3 ; Contents: This file contains soft reset subroutine
4 ;
5
6 ;--------------------------------------------------------------------------
7
8
9 public softReset
10 ;$include (fx2regs.inc)
+1 11 ;-----------------------------------------------------------------------------
+1 12 ; File: FX2regs.inc
+1 13 ; Contents: EZ-USB FX2 register declarations and bit mask definitions.
+1 14 ; This file is the equivalent of fx2regs.h but for assembl
ey code
+1 15 ; Do not modify one without modifying the other.
+1 16 ;
+1 17 ; Copyright (c) 2000 Cypress Semiconductor, All rights reserved
+1 18 ;-----------------------------------------------------------------------------
+1 19
E400 +1 20 GPIF_WAVE_DATA XDATA 0xE400 ;
E480 +1 21 RES_WAVEDATA_END XDATA 0xE480 ;
+1 22
+1 23 ; General Configuration
+1 24
E600 +1 25 CPUCS XDATA 0xE600 ; Control & Status
E601 +1 26 IFCONFIG XDATA 0xE601 ; Interface Configuration
E602 +1 27 PINFLAGSAB XDATA 0xE602 ; FIFO FLAGA and FLAGB Assignments
E603 +1 28 PINFLAGSCD XDATA 0xE603 ; FIFO FLAGC and FLAGD Assignments
E604 +1 29 FIFORESET XDATA 0xE604 ; Restore FIFOS to default state
E605 +1 30 BREAKPT XDATA 0xE605 ; Breakpoint
E606 +1 31 BPADDRH XDATA 0xE606 ; Breakpoint Address H
E607 +1 32 BPADDRL XDATA 0xE607 ; Breakpoint Address L
E608 +1 33 UART230 XDATA 0xE608 ; 230 Kbaud clock for T0,T1,T2
E609 +1 34 FIFOPINPOLAR XDATA 0xE609 ; FIFO polarities
E60A +1 35 REVID XDATA 0xE60A ; Chip Revision
E60B +1 36 REVCTL XDATA 0xE60B ; Chip Revision Control
+1 37
+1 38 ; Endpoint Configuration
+1 39
E610 +1 40 EP1OUTCFG XDATA 0xE610 ; Endpoint 1-OUT Configuration
E611 +1 41 EP1INCFG XDATA 0xE611 ; Endpoint 1-IN Configuration
E612 +1 42 EP2CFG XDATA 0xE612 ; Endpoint 2 Configuration
E613 +1 43 EP4CFG XDATA 0xE613 ; Endpoint 4 Configuration
E614 +1 44 EP6CFG XDATA 0xE614 ; Endpoint 6 Configuration
E615 +1 45 EP8CFG XDATA 0xE615 ; Endpoint 8 Configuration
E618 +1 46 EP2FIFOCFG XDATA 0xE618 ; Endpoint 2 FIFO configuration
E619 +1 47 EP4FIFOCFG XDATA 0xE619 ; Endpoint 4 FIFO configuration
E61A +1 48 EP6FIFOCFG XDATA 0xE61A ; Endpoint 6 FIFO configuration
E61B +1 49 EP8FIFOCFG XDATA 0xE61B ; Endpoint 8 FIFO configuration
E620 +1 50 EP2AUTOINLENH XDATA 0xE620 ; Endpoint 2 Packet Length H (IN only)
E621 +1 51 EP2AUTOINLENL XDATA 0xE621 ; Endpoint 2 Packet Length L (IN only)
E622 +1 52 EP4AUTOINLENH XDATA 0xE622 ; Endpoint 4 Packet Length H (IN only)
E623 +1 53 EP4AUTOINLENL XDATA 0xE623 ; Endpoint 4 Packet Length L (IN only)
E624 +1 54 EP6AUTOINLENH XDATA 0xE624 ; Endpoint 6 Packet Length H (IN only)
E625 +1 55 EP6AUTOINLENL XDATA 0xE625 ; Endpoint 6 Packet Length L (IN only)
E626 +1 56 EP8AUTOINLENH XDATA 0xE626 ; Endpoint 8 Packet Length H (IN only)
E627 +1 57 EP8AUTOINLENL XDATA 0xE627 ; Endpoint 8 Packet Length L (IN only)
AX51 MACRO ASSEMBLER RESET 10/12/07 16:09:52 PAGE 2
E630 +1 58 EP2FIFOPFH XDATA 0xE630 ; EP2 Programmable Flag trigger H
E631 +1 59 EP2FIFOPFL XDATA 0xE631 ; EP2 Programmable Flag trigger L
E632 +1 60 EP4FIFOPFH XDATA 0xE632 ; EP4 Programmable Flag trigger H
E633 +1 61 EP4FIFOPFL XDATA 0xE633 ; EP4 Programmable Flag trigger L
E634 +1 62 EP6FIFOPFH XDATA 0xE634 ; EP6 Programmable Flag trigger H
E635 +1 63 EP6FIFOPFL XDATA 0xE635 ; EP6 Programmable Flag trigger L
E636 +1 64 EP8FIFOPFH XDATA 0xE636 ; EP8 Programmable Flag trigger H
E637 +1 65 EP8FIFOPFL XDATA 0xE637 ; EP8 Programmable Flag trigger L
E640 +1 66 EP2ISOINPKTS XDATA 0xE640 ; EP2 (if ISO) IN Packets per frame (1-3)
E641 +1 67 EP4ISOINPKTS XDATA 0xE641 ; EP4 (if ISO) IN Packets per frame (1-3)
E642 +1 68 EP6ISOINPKTS XDATA 0xE642 ; EP6 (if ISO) IN Packets per frame (1-3)
E643 +1 69 EP8ISOINPKTS XDATA 0xE643 ; EP8 (if ISO) IN Packets per frame (1-3)
E648 +1 70 INPKTEND XDATA 0xE648 ; Force IN Packet End
E649 +1 71 OUTPKTEND XDATA 0xE649 ; Force OUT Packet End
+1 72
+1 73 ; Interrupts
+1 74
E650 +1 75 EP2FIFOIE XDATA 0xE650 ; Endpoint 2 Flag Interrupt Enable
E651 +1 76 EP2FIFOIRQ XDATA 0xE651 ; Endpoint 2 Flag Interrupt Request
E652 +1 77 EP4FIFOIE XDATA 0xE652 ; Endpoint 4 Flag Interrupt Enable
E653 +1 78 EP4FIFOIRQ XDATA 0xE653 ; Endpoint 4 Flag Interrupt Request
E654 +1 79 EP6FIFOIE XDATA 0xE654 ; Endpoint 6 Flag Interrupt Enable
E655 +1 80 EP6FIFOIRQ XDATA 0xE655 ; Endpoint 6 Flag Interrupt Request
E656 +1 81 EP8FIFOIE XDATA 0xE656 ; Endpoint 8 Flag Interrupt Enable
E657 +1 82 EP8FIFOIRQ XDATA 0xE657 ; Endpoint 8 Flag Interrupt Request
E658 +1 83 IBNIE XDATA 0xE658 ; IN-BULK-NAK Interrupt Enable
E659 +1 84 IBNIRQ XDATA 0xE659 ; IN-BULK-NAK interrupt Request
E65A +1 85 NAKIE XDATA 0xE65A ; Endpoint Ping NAK interrupt Enable
E65B +1 86 NAKIRQ XDATA 0xE65B ; Endpoint Ping NAK interrupt Request
E65C +1 87 USBIE XDATA 0xE65C ; USB Int Enables
E65D +1 88 USBIRQ XDATA 0xE65D ; USB Interrupt Requests
E65E +1 89 EPIE XDATA 0xE65E ; Endpoint Interrupt Enables
E65F +1 90 EPIRQ XDATA 0xE65F ; Endpoint Interrupt Requests
E660 +1 91 GPIFIE XDATA 0xE660 ; GPIF Interrupt Enable
E661 +1 92 GPIFIRQ XDATA 0xE661 ; GPIF Interrupt Request
E662 +1 93 USBERRIE XDATA 0xE662 ; USB Error Interrupt Enables
E663 +1 94 USBERRIRQ XDATA 0xE663 ; USB Error Interrupt Requests
E664 +1 95 ERRCNTLIM XDATA 0xE664 ; USB Error counter and limit
E665 +1 96 CLRERRCNT XDATA 0xE665 ; Clear Error Counter EC[3..0]
E666 +1 97 INT2IVEC XDATA 0xE666 ; Interupt 2 (USB) Autovector
E667 +1 98 INT4IVEC XDATA 0xE667 ; Interupt 4 (FIFOS & GPIF) Autovector
E668 +1 99 INTSETUP XDATA 0xE668 ; Interrupt 2&4 Setup
+1 100
+1 101 ; Input/Output
+1 102
E670 +1 103 PORTACFG XDATA 0xE670 ; I/O PORTA Alternate Configuration
E671 +1 104 PORTCCFG XDATA 0xE671 ; I/O PORTC Alternate Configuration
E672 +1 105 PORTECFG XDATA 0xE672 ; I/O PORTE Alternate Configuration
E678 +1 106 I2CS XDATA 0xE678 ; Control & Status
E679 +1 107 I2DAT XDATA 0xE679 ; Data
E67A +1 108 I2CTL XDATA 0xE67A ; I2C Control
E67B +1 109 EXTAUTODAT1 XDATA 0xE67B ; Autoptr1 MOVX access
E67C +1 110 EXTAUTODAT2 XDATA 0xE67C ; Autoptr2 MOVX access
+1 111
+1 112 ; USB Control
+1 113
E680 +1 114 USBCS XDATA 0xE680 ; USB Control & Status
E681 +1 115 SUSPEND XDATA 0xE681 ; Put chip into suspend
E682 +1 116 WAKEUPCS XDATA 0xE682 ; Wakeup source and polarity
E683 +1 117 TOGCTL XDATA 0xE683 ; Toggle Control
E684 +1 118 USBFRAMEH XDATA 0xE684 ; USB Frame count H
E685 +1 119 USBFRAMEL XDATA 0xE685 ; USB Frame count L
E686 +1 120 MICROFRAME XDATA 0xE686 ; Microframe count, 0-7
E687 +1 121 FNADDR XDATA 0xE687 ; USB Function address
+1 122
+1 123 ; Endpoints
AX51 MACRO ASSEMBLER RESET 10/12/07 16:09:52 PAGE 3
+1 124
E68A +1 125 EP0BCH XDATA 0xE68A ; Endpoint 0 Byte Count H
E68B +1 126 EP0BCL XDATA 0xE68B ; Endpoint 0 Byte Count L
E68D +1 127 EP1OUTBC XDATA 0xE68D ; Endpoint 1 OUT Byte Count
E68F +1 128 EP1INBC XDATA 0xE68F ; Endpoint 1 IN Byte Count
E690 +1 129 EP2BCH XDATA 0xE690 ; Endpoint 2 Byte Count H
E691 +1 130 EP2BCL XDATA 0xE691 ; Endpoint 2 Byte Count L
E694 +1 131 EP4BCH XDATA 0xE694 ; Endpoint 4 Byte Count H
E695 +1 132 EP4BCL XDATA 0xE695 ; Endpoint 4 Byte Count L
E698 +1 133 EP6BCH XDATA 0xE698 ; Endpoint 6 Byte Count H
E699 +1 134 EP6BCL XDATA 0xE699 ; Endpoint 6 Byte Count L
E69C +1 135 EP8BCH XDATA 0xE69C ; Endpoint 8 Byte Count H
E69D +1 136 EP8BCL XDATA 0xE69D ; Endpoint 8 Byte Count L
E6A0 +1 137 EP0CS XDATA 0xE6A0 ; Endpoint Control and Status
E6A1 +1 138 EP1OUTCS XDATA 0xE6A1 ; Endpoint 1 OUT Control and Status
E6A2 +1 139 EP1INCS XDATA 0xE6A2 ; Endpoint 1 IN Control and Status
E6A3 +1 140 EP2CS XDATA 0xE6A3 ; Endpoint 2 Control and Status
E6A4 +1 141 EP4CS XDATA 0xE6A4 ; Endpoint 4 Control and Status
E6A5 +1 142 EP6CS XDATA 0xE6A5 ; Endpoint 6 Control and Status
E6A6 +1 143 EP8CS XDATA 0xE6A6 ; Endpoint 8 Control and Status
E6A7 +1 144 EP2FIFOFLGS XDATA 0xE6A7 ; Endpoint 2 Flags
E6A8 +1 145 EP4FIFOFLGS XDATA 0xE6A8 ; Endpoint 4 Flags
E6A9 +1 146 EP6FIFOFLGS XDATA 0xE6A9 ; Endpoint 6 Flags
E6AA +1 147 EP8FIFOFLGS XDATA 0xE6AA ; Endpoint 8 Flags
E6AB +1 148 EP2FIFOBCH XDATA 0xE6AB ; EP2 FIFO total byte count H
E6AC +1 149 EP2FIFOBCL XDATA 0xE6AC ; EP2 FIFO total byte count L
E6AD +1 150 EP4FIFOBCH XDATA 0xE6AD ; EP4 FIFO total byte count H
E6AE +1 151 EP4FIFOBCL XDATA 0xE6AE ; EP4 FIFO total byte count L
E6AF +1 152 EP6FIFOBCH XDATA 0xE6AF ; EP6 FIFO total byte count H
E6B0 +1 153 EP6FIFOBCL XDATA 0xE6B0 ; EP6 FIFO total byte count L
E6B1 +1 154 EP8FIFOBCH XDATA 0xE6B1 ; EP8 FIFO total byte count H
E6B2 +1 155 EP8FIFOBCL XDATA 0xE6B2 ; EP8 FIFO total byte count L
E6B3 +1 156 SUDPTRH XDATA 0xE6B3 ; Setup Data Pointer high address byte
E6B4 +1 157 SUDPTRL XDATA 0xE6B4 ; Setup Data Pointer low address byte
E6B5 +1 158 SUDPTRCTL XDATA 0xE6B5 ; Setup Data Pointer Auto Mode
E6B8 +1 159 SETUPDAT XDATA 0xE6B8 ; 8 bytes of SETUP data
+1 160
+1 161 ; GPIF
+1 162
E6C0 +1 163 GPIFWFSELECT XDATA 0xE6C0 ; Waveform Selector
E6C1 +1 164 GPIFIDLECS XDATA 0xE6C1 ; GPIF Done, GPIF IDLE drive mode
E6C2 +1 165 GPIFIDLECTL XDATA 0xE6C2 ; Inactive Bus, CTL states
E6C3 +1 166 GPIFCTLCFG XDATA 0xE6C3 ; CTL OUT pin drive
E6C4 +1 167 GPIFADRH XDATA 0xE6C4 ; GPIF Address H
E6C5 +1 168 GPIFADRL XDATA 0xE6C5 ; GPIF Address L
+1 169
+1 170
E6CE +1 171 GPIFTCB3 XDATA 0xE6CE ; GPIF Transaction Count Byte 3
E6CF +1 172 GPIFTCB2 XDATA 0xE6CF ; GPIF Transaction Count Byte 2
E6D0 +1 173 GPIFTCB1 XDATA 0xE6D0 ; GPIF Transaction Count Byte 1
E6D1 +1 174 GPIFTCB0 XDATA 0xE6D1 ; GPIF Transaction Count Byte 0
+1 175
+1 176
E6D0 +1 177 EP2GPIFTCH EQU GPIFTCB1 ; these are here for backwards compatibility
E6D1 +1 178 EP2GPIFTCL EQU GPIFTCB0 ; before REVE silicon (ie. REVB and REVD)
E6D0 +1 179 EP4GPIFTCH EQU GPIFTCB1 ; these are here for backwards compatibility
E6D1 +1 180 EP4GPIFTCL EQU GPIFTCB0 ; before REVE silicon (ie. REVB and REVD)
E6D0 +1 181 EP6GPIFTCH EQU GPIFTCB1 ; these are here for backwards compatibility
E6D1 +1 182 EP6GPIFTCL EQU GPIFTCB0 ; before REVE silicon (ie. REVB and REVD)
E6D0 +1 183 EP8GPIFTCH EQU GPIFTCB1 ; these are here for backwards compatibility
E6D1 +1 184 EP8GPIFTCL EQU GPIFTCB0 ; before REVE silicon (ie. REVB and REVD)
+1 185
+1 186
+1 187 ; EP2GPIFTCH XDATA 0xE6D0 ; EP2 GPIF Transaction Count High
+1 188 ; EP2GPIFTCL XDATA 0xE6D1 ; EP2 GPIF Transaction Count Low
E6D2 +1 189 EP2GPIFFLGSEL XDATA 0xE6D2 ; EP2 GPIF Flag select
AX51 MACRO ASSEMBLER RESET 10/12/07 16:09:52 PAGE 4
E6D3 +1 190 EP2GPIFPFSTOP XDATA 0xE6D3 ; Stop GPIF EP2 transaction on prog. flag
E6D4 +1 191 EP2GPIFTRIG XDATA 0xE6D4 ; EP2 FIFO Trigger
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