📄 periph.lst
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C51 COMPILER V7.50 PERIPH 10/12/2007 17:05:45 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE PERIPH
OBJECT MODULE PLACED IN periph.OBJ
COMPILER INVOKED BY: d:\Keil\C51\BIN\C51.EXE periph.c OBJECTADVANCED OPTIMIZE(11,SIZE) REGFILE(.\nand_fw2k.ORC) BROWSE O
-RDER INCDIR(c:\cypress\usb\target\inc) DEFINE(NAND_2K) DEBUG
line level source
1 #pragma NOIV // Do not generate interrupt vectors
2
3 //-----------------------------------------------------------------------------
4 // File: periph.c
5
6 //--------------------------------------------------------------------------
7 #include "globals.h"
8
9 //-----------------------------------------------------------------------------
10 // Hardware/Software Initialization will be done here
11 // Search for USER_INIT and modify the IOD, OED, OEA for addition HW
12 // Modification
13 //-----------------------------------------------------------------------------
14 void TD_Init(void) // Called once at startup
15 {
16 1 MPAGE = 0xe6; // Map to Hardware register page 0xE600
17 1
18 1 IFCONFIG = IFCONFIG_DEFAULT;
19 1 CPUCS = 0x14; // set clock to 48MHz.
20 1
21 1 // Enable both autoptrs. ONLY use AUTOPTR2 for writing small amounts of data
22 1 AUTOPTRSETUP = 0x7;
23 1 AUTOPTRH2 = MSB(EP4FIFOBUF);
24 1
25 1 IT0 = 0; // Make Interrupt 0 level triggered
26 1 FLOWSTATE = 0x00; // turn off flowstate
27 1 FIFOPINPOLAR = 0x00; // ff pin is active low
28 1 PINFLAGSAB = 0x00; // FLAGA PF for FIFO selected by FIFOADR[1..0]
29 1 PINFLAGSCD = 0x00; // FLAGB FF for FIFO selected by FIFOADR[1..0]
30 1
31 1 // GPIF and CTL configuration
32 1 GPIFCTLCFG = 0x0; //
33 1 GPIFIDLECS = 0; // tristate data bus during idle interval
34 1 EP2FIFOCFG = 0x00; // byte wide
35 1 EP6FIFOCFG = 0x00; // byte wide
36 1 EP8FIFOCFG = 0x00; // byte wide
37 1 EP2FIFOPFH = 0x00; // PF=0 when BC > PF -> Decis=0 (1 byte in FIFO)
38 1 EP2FIFOPFL = 0x00; // PF and BC refer to the current pkt -> PKTSTAT=0
39 1 EP2GPIFPFSTOP = 0; // Do not stop on PF
40 1 EP6GPIFFLGSEL = 0x01;
41 1 EP2GPIFFLGSEL = 0x01; // Empty for the EP2
42 1
43 1 // Single write is 3, Single read is 2, write is 1, Read is waveform 0
44 1 GPIFWFSELECT = 0xe4;
45 1 GPIFREADYCFG = 0x20; // RDY5 is the transaction count expired
46 1 GPIFIDLECTL = 0x7; // x111x111 - CTL3 not enabled
47 1 // ||||||||_CTL0 = 1 during idle
48 1 // |||||||__CTL1 = 1 during idle
49 1 // ||||||___CTL2 = 1 during idle
50 1 // ||||_____CTL0 output enable
51 1 // |||______CTL1 output enable
52 1 // ||_______CTL2 output enable
53 1
54 1 // Endpoint initialization
C51 COMPILER V7.50 PERIPH 10/12/2007 17:05:45 PAGE 2
55 1 EP2CFG = EP2CFG_DEFAULT;
56 1 EP4CFG = EP4CFG_DEFAULT;
57 1
58 1 EP4FIFOCFG = EP4FIFOCFG_DEFAULT; // Setup EP4 FIFO CFG
59 1 EP4GPIFFLGSEL = 0x02; // GPIF will use the full flag as the fifoflag
60 1
61 1 // mark all unused endpoints invalid - setting each reg to 0x22 instead of just clearing
62 1 // the valid bit to save code space. 0x22 basically sets all of these endpoints to
63 1 // not valid, bulk, double 512 buffered.
64 1 #ifdef HID
EP1INCFG = 0xb0; // Setup EP1 IN
#else
67 1 EP1INCFG =
68 1 #endif
69 1 EP1OUTCFG = EP8CFG = EP6CFG = 0x22;
70 1 P_EP6CFG = EP6CFG_IN_DEFAULT; // Use from inand.h
71 1 REVCTL = bmNOAUTOARM | bmSKIPCOMMIT; // Enable enhanced packet handling.
72 1 // requires us to use OUTPKTEND to arm OUT endpoint
73 1 // init state/reset variables
74 1 currentState = UNCONFIGURED;
75 1 phaseErrorState = 0;
76 1 CKCON = 0x10; // Zero wait state
77 1 LED0_OFF(); // turn off both LEDs
78 1 LED1_OFF();
79 1 P_ECCCFG = 0x00; // set the NAND ECC calculator to 256 byte mode
80 1
81 1 GPIFABORT = 0xff; // force GPIF goto idle
82 1 P_EP6BCH = 0xff; // default
83 1
84 1 // USER_INIT:
85 1 // - Default PortD: set all pins = output
86 1 // - Default PortE: set all pins = output, except pin 5.
87 1 // - 512 NAND FW: Only 2 NAND chip selects on PortD (PD0 and PD1)
88 1 // - 2K NAND FW: Support PD0-PD3
89 1 PORTECFG = 0;
90 1 OED = 0xFF; // NAND chip select use PD0-7
91 1 OEE = 0xFE; // NAND chip select use PD0-7
92 1 IOD = 0xFF;
93 1 OEA = 0xDF; // 1101 1111 -- PA5 (WP switch) is an input
94 1
95 1 //TM_ClearWTD();
96 1 // relocate descriptor data to halfKBuffer when we know it's the first time
97 1 // i.e. On POR, TR0=0 = firsttime
98 1 //UM_InitUART();
99 1
100 1 if (!TR0)
101 1 {
102 2 memset16(halfKBuffer+cHALF_BUFF_OFFSET, 0, (cNAND_CFG_LENGTH/16)); // clear all zeros
103 2 mymemmovexx(halfKBuffer, (char xdata *) &DeviceDscr, (WORD)&DscrEndOffset);
104 2 mymemmovexx(&GPIF_WAVE_DATA, (BYTE xdata *) WaveDataPioUDMA, 128); // load wave forms in memory
105 2 InitNAND(); // Only call this when POR
106 2 }
107 1 // reset the EP4 FIFO. If we are here as the result of a USB reset or MSC
108 1 // Reset Recovery, EP4 may need to be cleaned up.
109 1 P_FIFORESET = 0x04;
110 1 // arm the OUT endpoint. By default OUT endpoints come up unarmed.
111 1 ResetAndArmEp2();
112 1 }
113 //-----------------------------------------------------------------------------
114 // Task Dispatcher hooks:
115 // The following hooks are called by the task dispatcher.
116 // USB Mass storage Command Processing here
C51 COMPILER V7.50 PERIPH 10/12/2007 17:05:45 PAGE 3
117 //-----------------------------------------------------------------------------
118 void TD_Poll(void) // Called repeatedly while the device is idle
119 {
120 1 BYTE xdata cmd;
121 1 // check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
122 1 if((P_EP2CS & bmEPEMPTY)) return;
123 1
124 1 currentState = WAIT_FOR_CBW;
125 1 AUTOPTR1H = MSB(EP2FIFOBUF);
126 1 AUTOPTR1L = LSB(EP2FIFOBUF);
127 1
128 1 if ((P_XAUTODAT1 != 'U' || // Check for "USBC"
129 1 P_XAUTODAT1 != 'S' ||
130 1 P_XAUTODAT1 != 'B' ||
131 1 P_XAUTODAT1 != 'C')|| (EP2BC != 31)
132 1 )
133 1 {
134 2 P_EP2CS = P_EP4CS = bmEPSTALL;
135 2 phaseErrorState = 1;
136 2 return;
137 2 }
138 1
139 1 LED0_ON();
140 1 *(((BYTE *) &cbwTagLow)+0) = P_XAUTODAT1;
141 1 *(((BYTE *) &cbwTagLow)+1) = P_XAUTODAT1;
142 1 *(((BYTE *) &cbwTagHi)+0) = P_XAUTODAT1;
143 1 *(((BYTE *) &cbwTagHi)+1) = P_XAUTODAT1;
144 1
145 1 // Get the length (convert from little endian)
146 1 *(((BYTE *) &dataTransferLen)+3) = P_XAUTODAT1;
147 1 *(((BYTE *) &dataTransferLen)+2) = P_XAUTODAT1; // "Residue"
148 1 *(((BYTE *) &dataTransferLen)+1) = P_XAUTODAT1; // "Residue"
149 1 *(((BYTE *) &dataTransferLen)+0) = P_XAUTODAT1; // "Residue"
150 1
151 1 directionIn = P_XAUTODAT1 & 0x80;
152 1 #ifdef USE_2LUN
bLUN1 = P_XAUTODAT1; // extract LUN
#endif
155 1 AUTOPTR1L = LSB(EP2FIFOBUF+CBW_DATA_START+2);
156 1 ((BYTE *) &gNextLBA)[0] = P_XAUTODAT1;
157 1 ((BYTE *) &gNextLBA)[1] = P_XAUTODAT1;
158 1 ((BYTE *) &gNextLBA)[2] = P_XAUTODAT1;
159 1 ((BYTE *) &gNextLBA)[3] = P_XAUTODAT1;
160 1 P_XAUTODAT1;
161 1 ((BYTE *) &gSectorcount)[0] = P_XAUTODAT1;
162 1 ((BYTE *) &gSectorcount)[1] = P_XAUTODAT1;
163 1 bErr = 0;
164 1 cmd = EP2FIFOBUF[0xf];
165 1 if (gPartialCpy)
166 1 {
167 2 // if the current command is not a write to our expected LBA
168 2 // then complete the partial block write
169 2 if (!((cmd == WRITE_10) && (dwLBA == gNextLBA)))
170 2 {
171 3 NAND_PCPY(gPartialCpy, xLBA3);
172 3 gPartialCpy = 0; // Reset partial cpy
173 3 nEraseBlock();
174 3 DISABLE_NAND();
175 3 }
176 2
177 2 }
178 1
C51 COMPILER V7.50 PERIPH 10/12/2007 17:05:45 PAGE 4
179 1 #ifdef USE_2LUN
if (bLUN1)
gNextLBA += (gDriveCapacity+1); // adjust for next block
#endif
183 1
184 1 dwLBA = gNextLBA;
185 1
186 1 switch(cmd)
187 1 {
188 2 // -- Read that starts after the end of the disk
189 2 // -- Read that starts inside the disk and continues beyond the end of the disk
190 2 // -- Unrecoverable ECC error
191 2 // case READ_06:
192 2 case READ_10:
193 2 // Add support for BOT test
194 2 cmd = xFerLen2>>1;
195 2 if (xFerLen1&1) cmd |= 0x80;
196 2 if ((cmd != xSector) || bEject || !directionIn)
197 2 {
198 3 failedIn();
199 3 cmd = USBS_FAILED;
200 3 break;
201 3 }
202 2 nReadPages();
203 2 cmd = ChkErr();
204 2 break;
205 2 //case WRITE_06:
206 2 case WRITE_10:
207 2 case WRITE_AND_VERIFY_10:
208 2 P_OUTPKTEND = 0x82;
209 2 // This check doesn't seem to be required by Windows. They will read and obey the WP
210 2 // state reported in the mode_sense data. This code is here for SCSI passthrough-enabled
211 2 // programs and other OSes.
212 2 if ( (
213 2 #ifndef NO_WP
214 2 (bWriteProtectEnable && !NAND_WP_SWITCH) ||
215 2 #endif
216 2 bEject) || // Read the (active low) WP switch if it's enabled
217 2 (xFerLen2>>1 != (xSector&0x7f)) // BOT: if (dataTransferLen/512 != gSectorcount)
218 2 )
219 2 {
220 3 sensePtr = senseWriteProtected;
221 3 stallEP2OUT();
222 3 cmd = USBS_FAILED;
223 3 break;
224 3 }
225 2 nWritePages();
226 2 cmd = ChkErr();
227 2 break;
228 2 default:
229 2 cmd = IDECommand();
230 2 break;
231 2 }
232 1 sendUSBS(cmd);
233 1 LED0_OFF();
234 1 }
235
236 //-----------------------------------------------------------------------------
237 // Handle NAND Error report here
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