📄 inand.h
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NAND_CLE=1, P_XGPIFSGLDATLX=cNAND_READ_START, NAND_CLE=0;\
}
#define n2k_wadd(a, msk) \
{ \
NAND_CLE=1,P_XGPIFSGLDATLX=cNAND_WRITE_DATA, NAND_CLE=0; \
NAND_ALE = 1, P_XGPIFSGLDATLX = nadd0[msk]; \
P_XGPIFSGLDATLX = nadd1[msk]; \
P_XGPIFSGLDATLX = ((BYTE *)&a)[3]; \
P_XGPIFSGLDATLX = ((BYTE *)&a)[2]; \
P_XGPIFSGLDATLX = ((BYTE *)&a)[1]; \
NAND_ALE = 0; \
}
#define n2k_set_radd() \
{ \
NAND_CLE=1,P_XGPIFSGLDATLX=cNAND_READ_DATA, NAND_CLE=0; \
NAND_ALE = 1, P_XGPIFSGLDATLX = 0; \
_nop_(); \
P_XGPIFSGLDATLX = 0; \
P_XGPIFSGLDATLX = ((BYTE *)&gPhyAdd)[3]; \
P_XGPIFSGLDATLX = ((BYTE *)&gPhyAdd)[2]; \
P_XGPIFSGLDATLX = ((BYTE *)&gPhyAdd)[1]; \
NAND_ALE = 0; \
NAND_CLE=1, P_XGPIFSGLDATLX=cNAND_READ_START, NAND_CLE=0;\
}
//==========================================================================
// 512P NAND Set address
//==========================================================================
#define n512_setadd(c, a) \
{ \
NAND_CLE=1,P_XGPIFSGLDATLX=c, NAND_CLE=0; \
NAND_ALE = 1, P_XGPIFSGLDATLX = 0; \
P_XGPIFSGLDATLX = ((BYTE *)&a)[3]; \
P_XGPIFSGLDATLX = ((BYTE *)&a)[2]; \
P_XGPIFSGLDATLX = ((BYTE *)&a)[1]; \
NAND_ALE = 0; \
}
//==========================================================================
// NAND Erase Block command can be used in both 512P and 2KP
//==========================================================================
#define nand_blk_erase(a) \
{ \
nand_ready3(); \
NAND_CLE=1,P_XGPIFSGLDATLX=cNAND_ERASE, NAND_CLE=0; \
NAND_ALE = 1; \
P_XGPIFSGLDATLX = ((BYTE *)&a)[3]; \
P_XGPIFSGLDATLX = ((BYTE *)&a)[2]; \
P_XGPIFSGLDATLX = ((BYTE *)&a)[1]; \
NAND_ALE = 0; \
NAND_CLE=1,P_XGPIFSGLDATLX=cNAND_ERASE_FINISH, NAND_CLE=0; \
}
//==========================================================================
// Debug the Log2Phy variables
//==========================================================================
#ifndef DEBUG
#define DBUG_DUMP()
#else
#define DBUG_DUMP() \
{ \
*(xbyte*)0xe1e0 = gCurZone; \
*(xbyte*)0xe1e1 = z; \
*(xbyte*)0xe1e2 = zz; \
*(xbyte*)0xe1e3 = page; \
*(xword*)0xe1e4 = gDst; \
*(xword*)0xe1e6 = gSrc; \
*(xdword*)0xe1ec = gPhyAdd; \
*(xdword*)0xe1f0 = gSrcAdd; \
}
#endif
//==========================================================================
// Use FIFO6 as buffer
//==========================================================================
#define fifo6_in() P_FIFORESET=6, P_EP6CFG=EP6CFG_IN_DEFAULT
#define fifo6_out() P_FIFORESET=6,P_EP6BCL = P_EP6CFG = EP6CFG_OUT_DEFAULT
#define ARM_EP2() { P_OUTPKTEND = 2; _nop_(); P_OUTPKTEND = 2; }
//==========================================================================
// local define for speed optimize
//==========================================================================
#define xLBA3 (((BYTE *)&dwLBA)[3])
#define xFerLen2 (((BYTE *)&dataTransferLen)[2])
#define xFerLen1 (((BYTE *)&dataTransferLen)[1])
#define xSector (((BYTE *)&gSectorcount)[1])
#define xPhyAdd (((BYTE *)&gPhyAdd)[3])
#define xSrcAdd (((BYTE *)&gSrcAdd)[3])
#define nand_send_command(cmd) NAND_CLE=1, P_XGPIFSGLDATLX=cmd, NAND_CLE=0
#define nand_get(stat) (NAND_CLE=1, P_XGPIFSGLDATLX=cNAND_READ_STATUS, NAND_CLE=0, P_XGPIFSGLDATLX, stat= P_XGPIFSGLDATLNOX)
#define writePIO16(e, c) { P_GPIFTCB1=MSB(c),P_GPIFTCB0= LSB(c), GPIFTRIG=e, _nop_();while (!gpifIdle()); }
#define readPIO16(e,c) { P_GPIFTCB1=MSB(c),P_GPIFTCB0= LSB(c), GPIFTRIG=(4|e), _nop_(); while (!gpifIdle()); }
#define FifoRd readPIO16
#define FifoWr writePIO16
//==========================================================================
// NAND Definition stuff
//==========================================================================
#define cNAND_DSIZE (512-1) // adjust for both read/write
#define cNAND_REDUNDANT_SIZE (16-1)
#define cNAND_PSIZE (528-1)
#define cNAND_RSIZ 12-1
#define NAND_ATA_SECTOR_SIZE 512
#define cCFG_ECC_OFF 0x0a // ECC offset in the redundant area
#define NAND_SCSI_CMD_VENDOR_CBW 0xC8
#define EP4CFG_DEFAULT 0xE0 // valid, IN, BULK, 512, double
#define EP2CFG_DEFAULT 0xA2 // valid, OUT, BULK, 512, double
#define TOTAL_SECTORS 0x3E800 // 128MB
#define cMaxBlkChk 24 // max 24 blocks
#define cINQUIRY_OFFSET 0x10
#define cINQUIRY_LENGTH 0x20 // INQUIRY Length
#define cVID_OFFSET 0
#define cHALF_BUFF_OFFSET 0x100 // offset for half buffer
#define cSTRING_OFFSET 0x30 // String offset from Vendor Config page
#define cNAND_CFG_LENGTH 0xE0 // From Inquiry offset
#define cMaxBlock 1024 // number of block in a Zone
#define cMaxBlock2N 10 // 2^10 = 1024
#define cMaxLogical 1000 // maximum logical per block
#define cBLK_INIT 0x0400 // block init
#define cBLK_aMSK (0x03ff|cBLK_INIT) // bit0-10 block address mask: valid 0-1023
#ifdef NAND_2K
#define cMaxZone 4 // maximun zone for 2K NAND is 4
#define NAND_PCPY nNandMove
#else
#define cMaxZone 8 // maximun zone for 512 is 8
#define NAND_PCPY nCopyPages
#endif
#define cRedundantSize 16
#define cBLK_USE 0x8000 // bit15=1=use else free
#define cBLK_CFG 0x4000 // Config Block or other cases
#define cBLK_ECC 0x2000 // check for repeat ECC error
#define cBLK_BAD 0x4000 // Bad Block
#define cBLK_uMSK (cBLK_USE|cBLK_CFG) // both bits are cleared = Block Free
#define c512PageSize 32
#define c2KPageSize 64
#define c2KPageSize2N 6
#define c512PageSize2N 5
#define cAddOffset 8
#define cECCOffset 2
#define c1Gbit_2N 0xd // 2^13 = 8192
#define c512Mbit_2N 0xc // 2^12 = 4096
#define ECCBUF 0xE62A
#define EP4FIFO (0xF400+cECCOffset)
#define cEP6FIFO (EP6FIFOBUF+512+cECCOffset)
#define cTOSHIBA_ID 0x98
#define cST_ID 0x20
#define cHYNIX_ID 0xad
#define cSAMSUNG_ID 0xec
//==========================================================================
// Local defines from the mass storage class spec
//==========================================================================
#define SC_MASS_STORAGE_RESET 0xff
#define SC_GET_MAX_LUN 0xfe
#define SC_HID_SET_IDLE 0xa
#define CBW_TAG 4
#define CBW_DATA_TRANSFER_LEN_LSB 8
#define CBW_DATA_TRANSFER_LEN_MSB 9
#define CBW_FLAGS 12
#define CBW_FLAGS_DIR_BIT 0x80
#define CBW_LUN 13
#define CBW_CBW_LEN 14
#define CBW_CBW_LEN_MASK 0xf
#define CBW_DATA_START 15
#define min(a,b) (((a)<(b))?(a):(b))
#define max(a,b) (((a)>(b))?(a):(b))
#define senseCRCError 0
#define senseInvalidFieldInCDB 1
#define senseOk 2
#define senseNoMedia 3
#define senseWriteFault 4
#define senseReadError 5
#define senseAddrNotFound 6
#define senseInvalidOpcode 7
#define senseInvalidLBA 8
#define senseInvalidParameter 9
#define senseCantEject 0xa
#define senseMediaChanged 0xb
#define senseDeviceReset 0xc
#define senseWriteProtected 0xd
#define USBS_PASSED 0
#define USBS_FAILED 1
#define USBS_PHASE_ERROR 2
// Fields in the INQUIRY
#define SCSI_INQUIRY_DEVICE_CLASS 0
#define SCSI_INQUIRY_REMOVABLE_BIT 0x80
#define SCSI_INQUIRY_REMOVABLE_BYTE 1
#define ATAPI_INQUIRY_REMOVABLE_BYTE 0
#define SCSI_INQUIRY_DATA_FORMAT 3
#define SCSI_INQUIRY_MANUFACTURER 8
#define ATAPI_INQUIRY_MANUFACTURER 27
#define SCSI_INQUIRY_MANUFACTURER_LEN 24
#define ATAPI_INQUIRY_REVISION 73
#define SCSI_INQUIRY_REVISION 32
#define SCSI_INQUIRY_REVISION_LEN 4
// SHORT_PACKET_BEFORE_STALL - Determines if a short packet is sent prior to
// the STALL ofan IN endpoint. The USB Mass Storage Class Bulk-Only
// Specification allows a device to send a short or zero-length IN packet
// prior to returning a STALL handshake for certain cases. Certain host
// controller drivers may require a short packet prior to STALL.
#define SHORT_PACKET_BEFORE_STALL TRUE
#define dataTransferLenLSW ((WORD *) (&dataTransferLen))[1]
#define pStr3Offset ((WORD)(halfKBuffer + (BYTE)&Str3Offset))
#define pVendorOffset ((WORD)(halfKBuffer + (BYTE)&VendorOffset))
#define pHighSpeedConfigDscr ((WORD)(halfKBuffer + (BYTE)&HighSpeedConfigDscrOffset))
#define pDscrVID ((WORD)(halfKBuffer + (BYTE)&DscrVIDOffset))
#define pLSB(offset) LSB((WORD)(halfKBuffer + (BYTE)&offset)) // general macro usage
#define HS_BULK_PACKET_SIZE 0x200
#define FS_BULK_PACKET_SIZE 0x40
#define BUFFER_SIZE 240 // halfKBuffer buffer size
#endif
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