📄 inand.h
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//-----------------------------------------------------------------------------
// Copyright (c) 2005 Cypress Semiconductor, Inc. All rights reserved
//
// File: inand.h
// Contents: NAND Flash definitions
//
// $Archive: /USB/atapifx2/NX2LP/SRC/CY3686FW/inand.h $
// $Date: 8/31/05 8:19a $
// $Revision: 2 $
//-----------------------------------------------------------------------------
//
// Copyright 2005, Cypress Semiconductor Corporation.
//
// This software is owned by Cypress Semiconductor Corporation (Cypress)
// and is protected by and subject to worldwide patent protection (United
// States and foreign), United States copyright laws and international
// treaty provisions. Cypress hereby grants to licensee a personal,
// non-exclusive, non-transferable license to copy, use, modify, create
// derivative works of, and compile the Cypress Source Code and derivative
// works for the sole purpose of creating custom software in support of
// licensee product to be used only in conjunction with a Cypress integrated
// circuit as specified in the applicable agreement. Any reproduction,
// modification, translation, compilation, or representation of this
// software except as specified above is prohibited without the express
// written permission of Cypress.
//
// Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND,EXPRESS OR IMPLIED,
// WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
// Cypress reserves the right to make changes without further notice to the
// materials described herein. Cypress does not assume any liability arising
// out of the application or use of any product or circuit described herein.
// Cypress does not authorize its products for use as critical components in
// life-support systems where a malfunction or failure may reasonably be
// expected to result in significant injury to the user. The inclusion of
// Cypress' product in a life-support systems application implies that the
// manufacturer assumes all risk of such use and in doing so indemnifies
// Cypress against all charges.
//
// Use may be limited by and subject to the applicable Cypress software
// license agreement.
//
//--------------------------------------------------------------------------
// Definition
//
// USE_2NAND When enable, it will support only 2 NAND chips
//
// NAND_2K enable this define when 2K NAND type is used
// disable this define when 512 NAND type is used
//
// NO_WP When enable, it will only support removable device
//
// NX2LP When enable, it will use NX2LP silicon, else it will use
// FX2LP silicon
//
// DEBUG When enable, will dump data for debugging
//
// USE_2LUN Support 2 LUNs
//
// CDROM_TYPE When enable, it will enable both CDROM in LUN1
//--------------------------------------------------------------------------
#ifndef CDROM_TYPE
#define cDriveType 0 // default cDriveType is removable device
#else
#define cDriveType 5 // enable CDROM type
#define USE_2LUN // only support this with multiple LUNs
#endif
#define cLUN1_Capacity 2048 // Allocate 2K sector for LUN1 => 1MB Size
#ifndef INAND_H
#define INAND_H
#define cFail 1
#define cOK 0
// defines for NAND project
// defines for NAND project
sbit NAND_CLE = 0x80+0; // PA0
sbit NAND_ALE = 0x80+1; // PA1
sbit NAND_LED0 = 0xB0+4; // PA2
sbit NAND_LED1 = 0xB0+5; // PA3
sbit NAND_WP = 0x80+2; // PA4
//sbit NAND_WP_SWITCH = 0x80+5; // PA5
#define NAND_WP_SWITCH (1)
//-----------------------------------------------------------------------------
// Use only 2 NAND chip select
//-----------------------------------------------------------------------------
#ifdef USE_2NAND
sbit CE0 = IOD^0; // Bank0
sbit CE1 = IOD^1; // Bank1
#define CE0_ON() CE0 = 0 // Assert NAND Bank0
#define CE0_OFF() CE0 = 1 // Negate NAND Bank0
#define CE1_ON() CE1 = 0 // Assert NAND Bank1
#define CE1_OFF() CE1 = 1 // Negate NAND Bank1
#define DISABLE_NAND() IOD |= 3 // Negate both Bank0 & Bank1
#else
//-----------------------------------------------------------------------------
// Use more than 2 NAND chips
//-----------------------------------------------------------------------------
#define DISABLE_NAND() IOD = 0xFF
#endif
#define LED0_ON() NAND_LED0 = 0
#define LED0_OFF() NAND_LED0 = 1
#define LED1_ON() NAND_LED1 = 0
#define LED1_OFF() NAND_LED1 = 1
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
#define cEP2 0 // Endpoint FIFO for GPIF
#define cEP4 1 // Endpoint FIFO for GPIF
#define cEP6 2 // Endpoint FIFO for GPIF
#define cEP8 3 // Endpoint FIFO for GPIF
#define EP6CFG_OUT_DEFAULT 0x1a // valid, OUT, ISO, 512, double
#define EP6CFG_IN_DEFAULT 0x5a // valid, IN, ISO, 512, 5a=quad buffer, 52=double
#define EP6FLGSEL_OUT_DEFAULT 0x02 // for EP6 OUTs, use the full flag
#define EP6FLGSEL_IN_DEFAULT 0x01 // for EP6 INs, use the empty flag
// Default GPIF timing will be 60ns
// This macro will enable 40ns
#define GPIF_40() *(xbyte*)0xe403 = *(xbyte*)0xe423 = 0x01
#define EP4FIFOCFG_DEFAULT (bmINFM | bmAUTOIN) // Read need to ajdust -1
#ifdef NAND_2K
//==========================================================================
// Write Redundant:
// This subroutine is faster the overhead of Setup the GPIF transfer
// 2K NAND need to finish to write all the un-used byte because the sub-page
// write
//==========================================================================
#define WriteRedundant() \
{ \
XGPIFSGLDATLX = 0xff; \
_nop_(); \
XGPIFSGLDATLX = 0xff; \
XGPIFSGLDATLX = P_ECC1B0[0]; \
XGPIFSGLDATLX = P_ECC1B0[1]; \
XGPIFSGLDATLX = P_ECC1B0[2]; \
XGPIFSGLDATLX = P_ECC1B0[3]; \
XGPIFSGLDATLX = P_ECC1B0[4]; \
XGPIFSGLDATLX = P_ECC1B0[5]; \
XGPIFSGLDATLX = MSB(gDst); \
XGPIFSGLDATLX = LSB(gDst); \
XGPIFSGLDATLX = MSB(gDst); \
XGPIFSGLDATLX = LSB(gDst); \
XGPIFSGLDATLX = 0xff; \
_nop_(); \
XGPIFSGLDATLX = 0xff; \
_nop_(); \
XGPIFSGLDATLX = 0xff; \
_nop_(); \
XGPIFSGLDATLX = 0xff; \
}
#else
//==========================================================================
// Write Redundant:
// This subroutine is faster the overhead of Setup the GPIF transfer
//==========================================================================
#define WriteRedundant() \
{ \
XGPIFSGLDATLX = 0xff; \
_nop_(); \
XGPIFSGLDATLX = 0xff; \
XGPIFSGLDATLX = P_ECC1B0[0]; \
XGPIFSGLDATLX = P_ECC1B0[1]; \
XGPIFSGLDATLX = P_ECC1B0[2]; \
XGPIFSGLDATLX = P_ECC1B0[3]; \
XGPIFSGLDATLX = P_ECC1B0[4]; \
XGPIFSGLDATLX = P_ECC1B0[5]; \
XGPIFSGLDATLX = MSB(gDst); \
XGPIFSGLDATLX = LSB(gDst); \
XGPIFSGLDATLX = MSB(gDst); \
XGPIFSGLDATLX = LSB(gDst); \
}
#endif
// the following are the NAND commands for 2K/512 page size NAND
#define cNAND_READ_DATA 0x00
#define cNAND_READ_START 0x30
#define cNAND_READ_REDUNDANT 0x50
#define cNAND_READ_STATUS 0x70
#define cNAND_READ_ID 0x90
#define cNAND_RESET 0xFF
#define cNAND_ERASE 0x60
#define cNAND_ERASE_FINISH 0xD0
#define cNAND_WRITE_DATA 0x80
#define cNAND_PROGRAM_PAGE 0x10
#define cNAND_PROGRAM_CACHE 0x15
#define cNAND_STATUS_BIT_FAIL 0x01
#define cNAND_STATUS_BIT_BUSY 0x40
#define cNAND_STATUS_BIT_WP 0x80
// bank0 and bank1 poll for ready
#define nand_ready0() while (!(P_GPIFREADYSTAT & 1)) // wait for bank0
#define nand_ready1() while (!(P_GPIFREADYSTAT & 2)) // wait for bank 1
#define nand_ready3() while ( (P_GPIFREADYSTAT & 3) != 3) // wait for both banks
#define cInterLeaveMsk 63 // 32 pages * 2 - 1
//==========================================================================
// 2KP NAND macros
//==========================================================================
#define n2k_set_wadd() \
{ \
nand_ready3(); \
NAND_CLE=1,P_XGPIFSGLDATLX=cNAND_WRITE_DATA, NAND_CLE=0; \
NAND_ALE = 1, P_XGPIFSGLDATLX = 0; \
_nop_(); \
P_XGPIFSGLDATLX = 0; \
P_XGPIFSGLDATLX = ((BYTE *)&gPhyAdd)[3]; \
P_XGPIFSGLDATLX = ((BYTE *)&gPhyAdd)[2]; \
P_XGPIFSGLDATLX = ((BYTE *)&gPhyAdd)[1]; \
NAND_ALE = 0; \
}
#define n2k_radd(a, msk) \
{ \
nand_ready3(); \
NAND_CLE=1,P_XGPIFSGLDATLX=cNAND_READ_DATA, NAND_CLE=0; \
NAND_ALE = 1, P_XGPIFSGLDATLX = nadd0[msk]; \
P_XGPIFSGLDATLX = nadd1[msk]; \
P_XGPIFSGLDATLX = ((BYTE *)&a)[3]; \
P_XGPIFSGLDATLX = ((BYTE *)&a)[2]; \
P_XGPIFSGLDATLX = ((BYTE *)&a)[1]; \
NAND_ALE = 0; \
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