📄 startup.lst
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E6D0 +1 178 EP8GPIFTCH EQU GPIFTCB1 ; these are here for backwards compatibility
E6D1 +1 179 EP8GPIFTCL EQU GPIFTCB0 ; before REVE silicon (ie. REVB and REVD)
+1 180
+1 181
+1 182 ; EP2GPIFTCH XDATA 0xE6D0 ; EP2 GPIF Transaction Count High
+1 183 ; EP2GPIFTCL XDATA 0xE6D1 ; EP2 GPIF Transaction Count Low
E6D2 +1 184 EP2GPIFFLGSEL XDATA 0xE6D2 ; EP2 GPIF Flag select
E6D3 +1 185 EP2GPIFPFSTOP XDATA 0xE6D3 ; Stop GPIF EP2 transaction on prog. flag
E6D4 +1 186 EP2GPIFTRIG XDATA 0xE6D4 ; EP2 FIFO Trigger
+1 187 ; EP4GPIFTCH XDATA 0xE6D8 ; EP4 GPIF Transaction Count High
+1 188 ; EP4GPIFTCL XDATA 0xE6D9 ; EP4 GPIF Transactionr Count Low
E6DA +1 189 EP4GPIFFLGSEL XDATA 0xE6DA ; EP4 GPIF Flag select
AX51 MACRO ASSEMBLER STARTUP 10/12/07 16:09:52 PAGE 4
E6DB +1 190 EP4GPIFPFSTOP XDATA 0xE6DB ; Stop GPIF EP4 transaction on prog. flag
E6DC +1 191 EP4GPIFTRIG XDATA 0xE6DC ; EP4 FIFO Trigger
+1 192 ; EP6GPIFTCH XDATA 0xE6E0 ; EP6 GPIF Transaction Count High
+1 193 ; EP6GPIFTCL XDATA 0xE6E1 ; EP6 GPIF Transaction Count Low
E6E2 +1 194 EP6GPIFFLGSEL XDATA 0xE6E2 ; EP6 GPIF Flag select
E6E3 +1 195 EP6GPIFPFSTOP XDATA 0xE6E3 ; Stop GPIF EP6 transaction on prog. flag
E6E4 +1 196 EP6GPIFTRIG XDATA 0xE6E4 ; EP6 FIFO Trigger
+1 197 ; EP8GPIFTCH XDATA 0xE6E8 ; EP8 GPIF Transaction Count High
+1 198 ; EP8GPIFTCL XDATA 0xE6E9 ; EP8GPIF Transaction Count Low
E6EA +1 199 EP8GPIFFLGSEL XDATA 0xE6EA ; EP8 GPIF Flag select
E6EB +1 200 EP8GPIFPFSTOP XDATA 0xE6EB ; Stop GPIF EP8 transaction on prog. flag
E6EC +1 201 EP8GPIFTRIG XDATA 0xE6EC ; EP8 FIFO Trigger
E6F0 +1 202 XGPIFSGLDATH XDATA 0xE6F0 ; GPIF Data H (16-bit mode only)
E6F1 +1 203 XGPIFSGLDATLX XDATA 0xE6F1 ; Read/Write GPIF Data L & trigger transac
E6F2 +1 204 XGPIFSGLDATLNOX XDATA 0xE6F2 ; Read GPIF Data L, no transac trigger
E6F3 +1 205 GPIFREADYCFG XDATA 0xE6F3 ; Internal RDY,Sync/Async, RDY5CFG
E6F4 +1 206 GPIFREADYSTAT XDATA 0xE6F4 ; RDY pin states
E6F5 +1 207 GPIFABORT XDATA 0xE6F5 ; Abort GPIF cycles
+1 208
+1 209 ; UDMA
+1 210
E6C6 +1 211 FLOWSTATE XDATA 0xE6C6 ; Defines GPIF flow state
E6C7 +1 212 FLOWLOGIC XDATA 0xE6C7 ; Defines flow/hold decision criteria
E6C8 +1 213 FLOWEQ0CTL XDATA 0xE6C8 ; CTL states during active flow state
E6C9 +1 214 FLOWEQ1CTL XDATA 0xE6C9 ; CTL states during hold flow state
E6CB +1 215 FLOWSTB XDATA 0xE6CB ; CTL/RDY Signal to use as master data strobe
E6CC +1 216 FLOWEDGE XDATA 0xE6CC ; Defines active master strobe edge
E6CD +1 217 FLOWSTBHPERIOD XDATA 0xE6CD ; Half Period of output master strobe
E60C +1 218 GPIFHOLDAMOUNT XDATA 0xE60C ; Data delay shift
E67D +1 219 UDMACRCH XDATA 0xE67D ; CRC Upper byte
E67E +1 220 UDMACRCL XDATA 0xE67E ; CRC Lower byte
E67F +1 221 UDMACRCQUAL XDATA 0xE67F ; UDMA In only, host terminated use only
+1 222
+1 223
+1 224 ; Debug/Test
+1 225
E6F8 +1 226 DBUG XDATA 0xE6F8 ; Debug
E6F9 +1 227 TESTCFG XDATA 0xE6F9 ; Test configuration
E6FA +1 228 USBTEST XDATA 0xE6FA ; USB Test Modes
E6FB +1 229 CT1 XDATA 0xE6FB ; Chirp Test--Override
E6FC +1 230 CT2 XDATA 0xE6FC ; Chirp Test--FSM
E6FD +1 231 CT3 XDATA 0xE6FD ; Chirp Test--Control Signals
E6FE +1 232 CT4 XDATA 0xE6FE ; Chirp Test--Inputs
+1 233
+1 234 ; Endpoint Buffers
+1 235
E740 +1 236 EP0BUF XDATA 0xE740 ; EP0 IN-OUT buffer
E780 +1 237 EP10UTBUF XDATA 0xE780 ; EP1-OUT buffer
E7C0 +1 238 EP1INBUF XDATA 0xE7C0 ; EP1-IN buffer
F000 +1 239 EP2FIFOBUF XDATA 0xF000 ; 512/1024-byte EP2 buffer (IN or OUT)
F400 +1 240 EP4FIFOBUF XDATA 0xF400 ; 512 byte EP4 buffer (IN or OUT)
F800 +1 241 EP6FIFOBUF XDATA 0xF800 ; 512/1024-byte EP6 buffer (IN or OUT)
FC00 +1 242 EP8FIFOBUF XDATA 0xFC00 ; 512 byte EP8 buffer (IN or OUT)
+1 243
+1 244 ;/*-----------------------------------------------------------------------------
+1 245 ; Special Function Registers (SFRs)
+1 246 ; The byte registers and bits defined in the following list are based
+1 247 ; on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
+1 248 ; If you modify the register definitions below, please regenerate the file
+1 249 ; "ezregs.inc" which includes the same basic information for assembly inclusion.
+1 250 ;-----------------------------------------------------------------------------*/
+1 251
0080 +1 252 IOA DATA 080H
0081 +1 253 SP DATA 081H
0082 +1 254 DPL DATA 082H
0083 +1 255 DPH DATA 083H
AX51 MACRO ASSEMBLER STARTUP 10/12/07 16:09:52 PAGE 5
0084 +1 256 DPL1 DATA 084H
0085 +1 257 DPH1 DATA 085H
0086 +1 258 DPS DATA 086H
+1 259 ; DPS
0080.6 +1 260 SEL BIT 086H+0H
0087 +1 261 PCON DATA 087H
+1 262 ; PCON
+1 263 ;IDLE BIT 087H+0H
+1 264 ;STOP BIT 087H+1H
+1 265 ;GF0 BIT 087H+2H
+1 266 ;GF1 BIT 087H+3H
+1 267 ;SMOD0 BIT 087H+7H
0088 +1 268 TCON DATA 088H
+1 269 ; TCON
0088.0 +1 270 IT0 BIT 088H+0H
0088.1 +1 271 IE0 BIT 088H+1H
0088.2 +1 272 IT1 BIT 088H+2H
0088.3 +1 273 IE1 BIT 088H+3H
0088.4 +1 274 TR0 BIT 088H+4H
0088.5 +1 275 TF0 BIT 088H+5H
0088.6 +1 276 TR1 BIT 088H+6H
0088.7 +1 277 TF1 BIT 088H+7H
0089 +1 278 TMOD DATA 089H
+1 279 ; TMOD
+1 280 ;M00 BIT 089H+0H
+1 281 ;M10 BIT 089H+1H
+1 282 ;CT0 BIT 089H+2H
+1 283 ;GATE0 BIT 089H+3H
+1 284 ;M01 BIT 089H+4H
+1 285 ;M11 BIT 089H+5H
+1 286 ;CT1 BIT 089H+6H
+1 287 ;GATE1 BIT 089H+7H
008A +1 288 TL0 DATA 08AH
008B +1 289 TL1 DATA 08BH
008C +1 290 TH0 DATA 08CH
008D +1 291 TH1 DATA 08DH
008E +1 292 CKCON DATA 08EH
+1 293 ; CKCON
+1 294 ;MD0 BIT 089H+0H
+1 295 ;MD1 BIT 089H+1H
+1 296 ;MD2 BIT 089H+2H
+1 297 ;T0M BIT 089H+3H
+1 298 ;T1M BIT 089H+4H
+1 299 ;T2M BIT 089H+5H
+1 300 ;SPC_FNC DATA 08FH ; Was WRS in Reg320
+1 301 ; CKCON
+1 302 ;WRS BIT 08FH+0H
0090 +1 303 IOB DATA 090H
0091 +1 304 EXIF DATA 091H ; EXIF Bit Values differ from Reg320
+1 305 ; EXIF
+1 306 ;USBINT BIT 091H+4H
+1 307 ;I2CINT BIT 091H+5H
+1 308 ;IE4 BIT 091H+6H
+1 309 ;IE5 BIT 091H+7H
0092 +1 310 MPAGE DATA 092H
0098 +1 311 SCON0 DATA 098H
+1 312 ; SCON0
0098.0 +1 313 RI BIT 098H+0H
0098.1 +1 314 TI BIT 098H+1H
0098.2 +1 315 RB8 BIT 098H+2H
0098.3 +1 316 TB8 BIT 098H+3H
0098.4 +1 317 REN BIT 098H+4H
0098.5 +1 318 SM2 BIT 098H+5H
0098.6 +1 319 SM1 BIT 098H+6H
0098.7 +1 320 SM0 BIT 098H+7H
0099 +1 321 SBUF0 DATA 099H
AX51 MACRO ASSEMBLER STARTUP 10/12/07 16:09:52 PAGE 6
+1 322
009A +1 323 APTR1H DATA 09AH ; old name
009B +1 324 APTR1L DATA 09BH ; old name
009A +1 325 AUTOPTR1H DATA 09AH
009B +1 326 AUTOPTR1L DATA 09BH
009D +1 327 AUTOPTRH2 DATA 09DH
009E +1 328 AUTOPTRL2 DATA 09EH
00A0 +1 329 IOC DATA 0A0H
00A1 +1 330 INT2CLR DATA 0A1H
00A2 +1 331 INT4CLR DATA 0A2H
+1 332
00A8 +1 333 IE DATA 0A8H
+1 334 ; IE
00A8.0 +1 335 EX0 BIT 0A8H+0H
00A8.1 +1 336 ET0 BIT 0A8H+1H
00A8.2 +1 337 EX1 BIT 0A8H+2H
00A8.3 +1 338 ET1 BIT 0A8H+3H
00A8.4 +1 339 ES0 BIT 0A8H+4H
00A8.5 +1 340 ET2 BIT 0A8H+5H
00A8.6 +1 341 ES1 BIT 0A8H+6H
00A8.7 +1 342 EA BIT 0A8H+7H
+1 343
00AA +1 344 EP2468STAT DATA 0AAH
+1 345 ; EP2468STAT
+1 346 ;EP2E BIT 0AAH+0H
+1 347 ;EP2F BIT 0AAH+1H
+1 348 ;EP4E BIT 0AAH+2H
+1 349 ;EP4F BIT 0AAH+3H
+1 350 ;EP6E BIT 0AAH+4H
+1 351 ;EP6F BIT 0AAH+5H
+1 352 ;EP8E BIT 0AAH+6H
+1 353 ;EP8F BIT 0AAH+7H
+1 354
00AB +1 355 EP24FIFOFLGS DATA 0ABH
00AC +1 356 EP68FIFOFLGS DATA 0ACH
00AF +1 357 AUTOPTRSETUP DATA 0AFH
+1 358 ; AUTOPTRSETUP
+1 359 ;EXTACC BIT 0AFH+0H
+1 360 ;APTR1FZ BIT 0AFH+1H
+1 361 ;APTR2FZ BIT 0AFH+2H
+1 362
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