main.asm

Holtek audio decoder , headset 参考范例

;*******************************************************************************
;*
;*  (c) Copyright 2005, Holtek Semiconductor Inc.
;* 
;******************************************************************************/
;*******************************************************************************
;MODULE:	main.asm

;INITIAL:	11/14/2006

;AUTHOR:	C351  hongyuan lai

;NOTE:	 	HT82A850R Main Function

;VERSION:	0.01
;Function:
;key debounced	N
;oled		N
;volume adjust	Y
;2005/05/13     Update Key Debounce
;2005/05/25	Modify Pop noise
;*******************************************************************************

;***************************************************************
;Include File
;const.inc		user defined
;macro.asm		macro function
;***************************************************************
#include		ht82a850r.inc
#include		const.inc
#include		nRF24L01.inc
#include		macro.asm
#define			WaitBias	0

;***************************************************************
;           nRF transmit and receive FIFO  
;           each 64 bytes, 2 ms
;***************************************************************

RAMBank 1      DATA2
DATA2           .section                AT      40H             'DATA'
TX_FIFO_STACK		DB	64 DUP(?)
RX_FIFO_STACK		DB	64 DUP(?)
;====================================================================
;Variable Defined , DATA start from 40H
;====================================================================
RAMBank 0      DATA
DATA		.SECTION		AT	40H		'DATA'
;***************************************************************
;		USB ISR Var (backup during interrupt subroutine)
;***************************************************************
isr_usb_acc		DB		?
isr_usb_status		DB		?
isr_usb_mp1		DB		?
isr_usb_mp0		DB		?
isr_usb_tblp		DB		?
isr_usb_bp		DB		?
;***************************************************************
;		Timer0 ISR Var (backup during interrupt subroutine)
;***************************************************************
isr_tmr0_acc		DB		?
isr_tmr0_status		DB		?
isr_tmr0_mp1		DB		?
isr_tmr0_mp0		DB		?
isr_tmr0_tblp		DB		?
isr_tmr0_bp		DB		?
;***************************************************************
;		Timer1 ISR Var (backup during interrupt subroutine)
;***************************************************************
isr_tmr1_acc		DB		?
isr_tmr1_status		DB		?
isr_tmr1_mp1		DB		?
isr_tmr1_mp0		DB		?
isr_tmr1_tblp		DB		?
isr_tmr1_bp		DB		?
;***************************************************************
;		Play ISR Var (backup during interrupt subroutine)
;***************************************************************
isr_play_acc		DB		?
isr_play_status		DB		?
isr_play_mp1		DB		?
isr_play_mp0		DB		?
isr_play_tblp		DB		?
isr_play_bp		DB		?
;***************************************************************
;		Rec ISR Var (backup during interrupt subroutine)
;***************************************************************
isr_rec_acc		DB		?
isr_rec_status		DB		?
isr_rec_mp1		DB		?
isr_rec_mp0		DB		?
isr_rec_tblp		DB		?
isr_rec_bp		DB		?
;***************************************************************
;		Delay parameter
;***************************************************************
Delay_1			DB		?
Delay_2			DB		?
Delay_3			DB		?

;***************************************************************
;USB FIFO Variable
;USB_Interface : to save usb current interface number
;USB_Interface_Alt : to save usb current alternate of interface number
;USB_Configuration : to save USB configuration number
;FIFO_ADDR     : to save USB ADDRESS
;Loop_Counter , Data_Count , Data_Start : control_read variable
;***************************************************************
;For FIFO Access
;------------------------------------------------
;voice control
INC_Counter			db	?
DEC_Counter			db	?


;FIFO
FIFO_TEMP			db	?

;Audio
PortC_data			db	?
bFlag_Audio_Mute		dbit
bFlag_Mic_Mute			dbit
Volume1				db	?
Volume2				db	?
bFlag_Mute_Detect		dbit		
bFlag_INC_Detect		dbit		
bFlag_DEC_Detect		dbit
bFlag_Play_Enable		dbit		; 2006.7.24
Flag_Audio_Control		db	?	; 0 0 muteH muteL incH incL decH decL


Key_Process			db	?
Key_CheckIn			db	?
Key_Counter			db	?
Key_Temp			db	?
Key_IncCounter			db	?
Key_DecCounter			db	?
;MODE_CTRL_TEMP  		db    	?	
TMR1_KEY_FG			dbit

;---------------
ADC_POR_FG			dbit
;---------------


;====== nRF24L01 ========================
;--use for address initial/setup/save/change
TX_FIFO_ADDR			DB	?
TX_FIFO_ADDR1			DB	?
RX_FIFO_ADDR			DB	?
RX_FIFO_ADDR1			DB	?
FIFO_COUNTER			DB	?
DAC_COUNTER			DB	?
DAC_FIFO_COUNTER		DB	?
ADC_FIFO_COUNTER		DB	?
IRQ_counter			DB	?
TX_FIFO_ADDR_temp		DB	?
RX_FIFO_ADDR_temp		DB	?
RX_FIFO_Status			DB	?
TX_key_code			DB	?
channel_1			DB	?
channel_2			DB	?

bFlag_IRQ_Flag			DBIT
bFlag_IRQ_Flag2			DBIT
bFlag_TX_FIFO			DBIT
RX_FIFO_Flag			DBIT
bFlag_TX_FIFO_Select		DBIT
bFlag_TX_FIFO_Select1		DBIT
bFlag_RX_FIFO_Select		DBIT
bFlag_RX_FIFO_Select1		DBIT
bFlag_TX_Mode			DBIT
bFlag_RX_Mode			DBIT
bFlag_RX_SPI_ok			DBIT
bFlag_8k_fast			DBIT

;----use for payload
bFlag_End_SPI_Operation   	DBIT	

;---general variant
temp_num			DB	?	;general use for SPI counter
table_data			DB	?	;initial table
COMMAND_L			DB	?	;second send data via SPI
COMMAND_H			DB	?	;first 	send data via SPI
RF_number			DB	?

;---TX/RX ADDR WRITE
TX_ADDRESS_Select		DB	?
RX_ADDRESS_Select		DB	?
nRF_ADDR_value			DB	5  DUP(?)

#define 	AUDIO_8K 		1


;nRF 24L01
;extern		TX_RX_Switch:NEAR
;extern		nRF_TX_Transmit:NEAR
;extern		nRF_RX_Receive:NEAR
extern		nRF_initial:NEAR
extern		nRF_int:NEAR

;***************************************************************
;		MCU Interrupt Table
;***************************************************************


CODE            .section        AT 00H 'code'
		ORG		00H
		jmp		Start
		;ORG		04H
		;jmp		USB_ISR
		ORG		08H
		jmp		Timer_0_ISR
		ORG		0CH
		jmp		Timer_1_ISR
		ORG		10H
		jmp		AUDIO_INT_ISR		
		ORG		18H
		jmp		RECORD_INT_ISR

	;-----------------------------------------------------------
	; Start : ORG 20H 
	;-----------------------------------------------------------
ORG	20H
Start:
;---------------------------------------
;modify 2006-07-27
ADC_Power_On_Reset:
		set	AD_ENB 		;AD_ENB=1 =>ADC Power Down
		call  	Delay_20ms
		clr	AD_ENB 		;AD_ENB=0 =>ADC Power On
;---------------------------------------
		call	System_Initial
		call 	nRF_initial
	;-----------------------------------------------------------
	; Main LOOP Function  : 
	;-----------------------------------------------------------
Main:


Main_My_Function:
	;-----------------------------------------------------------
	; Here to add your another code !!
	;-----------------------------------------------------------
		clr wdt	
		NOP
;---------------------------------------------------	
		;modify 2006-07-27	
		SZ 	ADC_POR_FG
		JMP 	Main_End1			
		set	AD_ENB 		;AD_ENB=1 =>ADC Power Down
		call  	Delay_20ms
		clr	AD_ENB 		;AD_ENB=0 =>ADC Power On
		SET	ADC_POR_FG
;---------------------------------------------------
Main_End1:
		;;sz	NRF_IRQ
		;;jmp	Main_My_Function
		set	pa.0
		set	EPLAYI
Main_End2:
		;call	TX_RX_Switch
		;call	nRF_TX_Transmit
		;call	nRF_RX_Receive
		JMP	Main_End2

;***************************************************************
;		System Initial
;		1.ram_initial
;		1.Timer Initial
;		2.USB Config
;***************************************************************
System_Initial:
	;-----------------------------------------------------------
	; Debug
	;-----------------------------------------------------------
		clr wdt

	;-----------------------------------------------------------
	; Modify Pop Noise
	;-----------------------------------------------------------
		kmov WDTS,07h
		mov		a,WDTS
		mov		FIFO_TEMP,a

		mov		a,01010111b
		mov		WDTS,a

		clr		[02DH]

		
		mov		a,80H
		mov		[02EH],a
		nop
		nop
		set		[02FH].3
		nop
		nop
		clr		[02FH].3
		nop
		nop

		mov		a,FIFO_TEMP
		mov		WDTS,a
	;-----------------------------------------------------------
	; Wait Bais and ROUT LOUT Capacity rise about 1.98ms
	; delay time = 255*255*30*3(sdz,jmp) cycle * 0.3333us/cycle = 1.98 ms
	;-----------------------------------------------------------
	IF	WaitBias
		clr		pac

		clr		FIFO_OUT1
		clr		FIFO_OUT2
		clr		FIFO_OUT3
		mov		a,9		
		mov		FIFO_OUT3,a
		clr		pa



	System_Initial_Loop:
		clr wdt	
		sdz		FIFO_OUT1
		jmp		System_Initial_Loop
		sdz		FIFO_OUT2
		jmp		System_Initial_Loop		
		sdz		FIFO_OUT3
		jmp		System_Initial_Loop		
		nop
		clr wdt	
		set		pa
	ENDIF
	;-----------------------------------------------------------
	; Codec Limit
	;-----------------------------------------------------------
		clr		[02DH]
		set		[02EH]
	;-----------------------------------------------------------
	; ram_initial : clear the ram of bank 0
	;-----------------------------------------------------------
	ram_initial:	;clear RAM (040H--0FFH)
		MOV		A,040H
		MOV		MP0,A
		MOV		A,192
	ram_initial_next_addr:
		clr		wdt
		CLR		R0
		INC		MP0
		SDZ		acc
		JMP		ram_initial_next_addr

	ram_initial_1:	;clear RAM (040H--0FFH)
		MOV		A,040H
		MOV		MP1,A
		KMOV		TBLP,192
		kmov		BP,001h
	ram_initial_next_addr_1:
		clr		wdt
		KMOV		R1,080h
		INC		MP1
		SDZ		TBLP
		JMP		ram_initial_next_addr_1
		clr		BP	
			
	;-----------------------------------------------------------
	; timer_initial : do timer initial
	;-----------------------------------------------------------
	timer_initial:
		MOV 		A,82H		;  low to high edge trigger, internal timer mode
		MOV		TMR0C,A		;
		MOV		A,00H		; 1ms
		MOV		TMR0L,A		
		MOV		A,000H		
		MOV		TMR0H,A		

		mov		a,80H
		mov		TMR1C,a
		mov		a,00H
		mov		TMR1L,a
		mov		TMR1H,a

	;-----------------------------------------------------------
	; config_io_port :
	;-----------------------------------------------------------
		clr		pa
		;kmov		pac,0FEH
		
		IF 		UseMediaKey
			kmov		pac,Key_Defined
		ENDIF
		IFE		UseMediaKey
			kmov		pac,00000000b
		ENDIF
		
		clr		pb
		set		pbc
		clr		pc		;for volume control
		set		pcc

	;-----------------------------------------------------------
	; config_usb_speaker_register :
	;-----------------------------------------------------------
		clr		USVC		;mute & 0db
	
	;for test
		;set		DA_R_ENB	;Right Channel Disable	
		

	;-----------------------------------------------------------
	; config_usb : do usb config
	;-----------------------------------------------------------
	config_usb:
		CLR		INTC0
		;SET		INTC0.@INTC0_EEI		;enable USB
		SET		INTC0.@INTC0_EMI		;Global interrupt

		;set		MISC.@MISC_ISOEN	;ISO Output Interrupt Enable
		;set		MISC.@MISC_ISIEN	;ISO Input Interrupt Enable
		;clr		STALL
		clr		UCC.@UCC_SUSP2
		
		;SYSCLK
		;set			UCC.6	//set to 6 MHz

		set 		UCC.@UCC_USBCKEN
		nop
		;set		USC.@USC_V33C		;//pc start to send command

			
		if	AUDIO_8K
			set		MODE_CTRL.3
		endif
		
		clr wdt		
		RET

;***************************************************************
;		AUDIO_INT_ISR
;		
;		
;***************************************************************
AUDIO_INT_ISR:
		MOV		isr_play_acc,A		;save ACC
		MOV		A,STATUS
		MOV		isr_play_status,A	;save status
		MOV		A,MP1
		MOV		isr_play_mp1,A		;save mp1
		MOV		A,MP0
		MOV		isr_play_mp0,A		;save mp0
		MOV		A,TBLP
		MOV		isr_play_tblp,A		;save TBLP
		MOV		A,BP
		MOV		isr_play_bp,A		;save bp		

		;call		nRF_int			
		
		;------- RAM to DAC (play)
		xmov	FIFO_TEMP,WDTS			;save WDT
		xmov	WDTS,01010000b			;dac write mode  	
		mov     A,RX_FIFO_ADDR_temp		;RX ADDRESS start
		ADD     A,DAC_FIFO_COUNTER				
		mov     MP1,A				
		kmov	DAC_LIMIT_L,R1
		inc     MP1
	   	kmov	DAC_LIMIT_H,R1
		;------- write DAC trigger
		set	DAC_WR.3
		nop
		clr	DAC_WR.3
		nop	
		xmov	WDTS,FIFO_TEMP 

		;------- ADC to RAM (rec)
		mov     a,DAC_FIFO_COUNTER
		mov     mp1,a
		kmov    R1,RECORD_DATA_L
		inc     mp1
		kmov	R1,RECORD_DATA_H