sim.out

来自「ucos在xc167下的移植源程序」· OUT 代码 · 共 75 行

ATTENTION: TSIM is an ARCHITECTURAL MODEL.
CYCLE COUNTS are APPROXIMATE.

********************************************** 
banks:1   lines:16   ways:2   bits:256 speed:0 
********************************************** 
********************************************** 
banks:2   lines:128   ways:2   bits:128 speed:0
PARTITION 0: FROM 0xa0000000 UNTIL 0xa007ffff  7 Twait
PARTITION 1: FROM 0xa0080000 UNTIL 0xa00effff  7 Twait
PARTITION 2: FROM 0xa00f0000 UNTIL 0xa00f20ff  0 Twait
PARTITION 3: FROM 0xc0000000 UNTIL 0xc0001fff  0 Twait
PARTITION 4: FROM 0xd0000000 UNTIL 0xd0007fff  0 Twait


No interrupt config file specified

Reading internal peripheral registers

No peripheral config file specified

RESET PC = a0000000
InitMemorySpace called

RESET PC = a0000000
Simulation complete

**************** Simulation statistics ****************

Total number of instructions executed = 2260000
Total number of cycles run            = 17961664
Total number of seconds for execution = 2      seconds

total number of interrupts fired=0
No Dcache accesses

No Ccache accesses
Instruction histogram:		  %     (Num of instructions)
		MAC:		 0%       (0)
		JMPS:		 0%       (0)
		LOADS:		 0%       (0)
		STORES:		 0%       (0)
		ARITHMETIC:	100%       (2260000)
		SYS:	     0%       (0)
		MISC:	     0%       (0)

Data Register usage for 32 bit instructions: 

DR[00] = 0	DR[01] = 0	DR[02] = 0	DR[03] = 0
DR[04] = 0	DR[05] = 0	DR[06] = 0	DR[07] = 0
DR[08] = 0	DR[09] = 0	DR[10] = 0	DR[11] = 0
DR[12] = 0	DR[13] = 0	DR[14] = 0	DR[15] = 0

Address Register usage for 32 bit instructions: 

AR[00] = 0	AR[01] = 0	AR[02] = 0	AR[03] = 0
AR[04] = 0	AR[05] = 0	AR[06] = 0	AR[07] = 0
AR[08] = 0	AR[09] = 0	AR[10] = 0	AR[11] = 0
AR[12] = 0	AR[13] = 0	AR[14] = 0	AR[15] = 0

Data Register usage for 16 bit instructions:

DR[00] = 0	DR[01] = 0	DR[02] = 0	DR[03] = 0
DR[04] = 0	DR[05] = 0	DR[06] = 0	DR[07] = 0
DR[08] = 0	DR[09] = 0	DR[10] = 0	DR[11] = 0
DR[12] = 0	DR[13] = 0	DR[14] = 0	DR[15] = 8

Address Register usage for 16 bit instructions:

AR[00] = 0	AR[01] = 0	AR[02] = 0	AR[03] = 0
AR[04] = 0	AR[05] = 0	AR[06] = 0	AR[07] = 0
AR[08] = 0	AR[09] = 0	AR[10] = 0	AR[11] = 8
AR[12] = 0	AR[13] = 0	AR[14] = 0	AR[15] = 0