mb89201.h

单片机

#define DDR3_D36 ddr3.bit._D36
#define DDR3_D37 ddr3.bit._D37

extern __io RSFRSTR rsfr;   /*  Reset Flag Register */
#define RSFR rsfr.byte
#define RSFR_SFTR rsfr.bit._SFTR
#define RSFR_WDOG rsfr.bit._WDOG
#define RSFR_ERST rsfr.bit._ERST
#define RSFR_PONR rsfr.bit._PONR

extern __io PDR4STR pdr4;   /*  Port Data/Direction Registers Port 4+5 */
#define PDR4 pdr4.byte
#define PDR4_P40 pdr4.bit._P40
#define PDR4_P41 pdr4.bit._P41
#define PDR4_P42 pdr4.bit._P42
#define PDR4_P43 pdr4.bit._P43

extern __io DDR4STR ddr4;  
#define DDR4 ddr4.byte
#define DDR4_D40 ddr4.bit._D40
#define DDR4_D41 ddr4.bit._D41
#define DDR4_D42 ddr4.bit._D42
#define DDR4_D43 ddr4.bit._D43

extern __io OUT4STR out4;  
#define OUT4 out4.byte
#define OUT4_OUT40 out4.bit._OUT40
#define OUT4_OUT41 out4.bit._OUT41
#define OUT4_OUT42 out4.bit._OUT42
#define OUT4_OUT43 out4.bit._OUT43

extern __io PDR5STR pdr5;  
#define PDR5 pdr5.byte
#define PDR5_P50 pdr5.bit._P50

extern __io DDR5STR ddr5;  
#define DDR5 ddr5.byte
#define DDR5_D50 ddr5.bit._D50

extern __io RCR21STR rcr21;   /*  12bit PPG */
#define RCR21 rcr21.byte
#define RCR21_HSC0 rcr21.bit._HSC0
#define RCR21_HSC1 rcr21.bit._HSC1
#define RCR21_HSC2 rcr21.bit._HSC2
#define RCR21_HSC3 rcr21.bit._HSC3
#define RCR21_HSC4 rcr21.bit._HSC4
#define RCR21_HSC5 rcr21.bit._HSC5
#define RCR21_RCK0 rcr21.bit._RCK0
#define RCR21_RCK1 rcr21.bit._RCK1
#define RCR21_HSC rcr21.bitc._HSC
#define RCR21_RCK rcr21.bitc._RCK

extern __io RCR22STR rcr22;  
#define RCR22 rcr22.byte
#define RCR22_HSC6 rcr22.bit._HSC6
#define RCR22_HSC7 rcr22.bit._HSC7
#define RCR22_HSC8 rcr22.bit._HSC8
#define RCR22_HSC9 rcr22.bit._HSC9
#define RCR22_HSC10 rcr22.bit._HSC10
#define RCR22_HSC11 rcr22.bit._HSC11
#define RCR22_HSC rcr22.bitc._HSC

extern __io volatile IO_WORD rcr212;
#define RCR212 rcr212   

extern __io RCR23STR rcr23;  
#define RCR23 rcr23.byte
#define RCR23_SCL0 rcr23.bit._SCL0
#define RCR23_SCL1 rcr23.bit._SCL1
#define RCR23_SCL2 rcr23.bit._SCL2
#define RCR23_SCL3 rcr23.bit._SCL3
#define RCR23_SCL4 rcr23.bit._SCL4
#define RCR23_SCL5 rcr23.bit._SCL5
#define RCR23_RCEN rcr23.bit._RCEN
#define RCR23_SCL rcr23.bitc._SCL

extern __io RCR24STR rcr24;  
#define RCR24 rcr24.byte
#define RCR24_SCL6 rcr24.bit._SCL6
#define RCR24_SCL7 rcr24.bit._SCL7
#define RCR24_SCL8 rcr24.bit._SCL8
#define RCR24_SCL9 rcr24.bit._SCL9
#define RCR24_SCL10 rcr24.bit._SCL10
#define RCR24_SCL11 rcr24.bit._SCL11
#define RCR24_SCL rcr24.bitc._SCL

extern __io volatile IO_WORD rcr234;
#define RCR234 rcr234   

extern __io BZCRSTR bzcr;   /*  Buzzer Register */
#define BZCR bzcr.byte
#define BZCR_BZ0 bzcr.bit._BZ0
#define BZCR_BZ1 bzcr.bit._BZ1
#define BZCR_BZ2 bzcr.bit._BZ2
#define BZCR_BZ bzcr.bitc._BZ

extern __io TCCRSTR tccr;   /*  Timer and Capture */
#define TCCR tccr.byte
#define TCCR_EDGS0 tccr.bit._EDGS0
#define TCCR_EDGS1 tccr.bit._EDGS1
#define TCCR_TCMSK tccr.bit._TCMSK
#define TCCR_CCMSK tccr.bit._CCMSK
#define TCCR_CPIEN tccr.bit._CPIEN
#define TCCR_CFCLR tccr.bit._CFCLR
#define TCCR_CPIF tccr.bit._CPIF
#define TCCR_EDGS tccr.bitc._EDGS

extern __io TCR1STR tcr1;  
#define TCR1 tcr1.byte
#define TCR1_TSTR1 tcr1.bit._TSTR1
#define TCR1_TCS10 tcr1.bit._TCS10
#define TCR1_TCS11 tcr1.bit._TCS11
#define TCR1_TCS12 tcr1.bit._TCS12
#define TCR1_T1IEN tcr1.bit._T1IEN
#define TCR1_TFCR1 tcr1.bit._TFCR1
#define TCR1_TIF1 tcr1.bit._TIF1
#define TCR1_TCS1 tcr1.bitc._TCS1

extern __io TCR0STR tcr0;  
#define TCR0 tcr0.byte
#define TCR0_TSTR0 tcr0.bit._TSTR0
#define TCR0_TCS00 tcr0.bit._TCS00
#define TCR0_TCS01 tcr0.bit._TCS01
#define TCR0_TCS02 tcr0.bit._TCS02
#define TCR0_CINV tcr0.bit._CINV
#define TCR0_T0IEN tcr0.bit._T0IEN
#define TCR0_TFCR0 tcr0.bit._TFCR0
#define TCR0_TIF0 tcr0.bit._TIF0
#define TCR0_TCS0 tcr0.bitc._TCS0

extern __io volatile IO_BYTE tdr1;
#define TDR1 tdr1   

extern __io volatile IO_BYTE tdr0;
#define TDR0 tdr0   

extern __io volatile IO_BYTE tcph;
#define TCPH tcph   

extern __io volatile IO_BYTE tcpl;
#define TCPL tcpl   

extern __io TCR2STR tcr2;  
#define TCR2 tcr2.byte
#define TCR2_TSEL tcr2.bit._TSEL
#define TCR2_PEN tcr2.bit._PEN

extern __io CNTRSTR cntr;   /*  PWM Register */
#define CNTR cntr.byte
#define CNTR_TIE cntr.bit._TIE
#define CNTR_OE cntr.bit._OE
#define CNTR_TIR cntr.bit._TIR
#define CNTR_TPE cntr.bit._TPE
#define CNTR_P0 cntr.bit._P0
#define CNTR_P1 cntr.bit._P1
#define CNTR_PTX cntr.bit._PTX
#define CNTR_P cntr.bitc._P

extern __io volatile IO_BYTE comr;
#define COMR comr   

extern __io EIC1STR eic1;   /*  external interrupt - edge */
#define EIC1 eic1.byte
#define EIC1_EIE0 eic1.bit._EIE0
#define EIC1_SL00 eic1.bit._SL00
#define EIC1_SL01 eic1.bit._SL01
#define EIC1_EIR0 eic1.bit._EIR0
#define EIC1_EIE1 eic1.bit._EIE1
#define EIC1_SL10 eic1.bit._SL10
#define EIC1_SL11 eic1.bit._SL11
#define EIC1_EIR1 eic1.bit._EIR1
#define EIC1_SL0 eic1.bitc._SL0
#define EIC1_SL1 eic1.bitc._SL1

extern __io EIC2STR eic2;  
#define EIC2 eic2.byte
#define EIC2_EIE2 eic2.bit._EIE2
#define EIC2_SL20 eic2.bit._SL20
#define EIC2_SL21 eic2.bit._SL21
#define EIC2_EIR2 eic2.bit._EIR2
#define EIC2_SL2 eic2.bitc._SL2

extern __io SMCSTR smc;   /*  UART */
#define SMC smc.byte
#define SMC_SOE smc.bit._SOE
#define SMC_SCKE smc.bit._SCKE
#define SMC_SMDE smc.bit._SMDE
#define SMC_MC0 smc.bit._MC0
#define SMC_MC1 smc.bit._MC1
#define SMC_SBL smc.bit._SBL
#define SMC_PEN smc.bit._PEN
#define SMC_MC smc.bitc._MC

extern __io SRCSTR src;  
#define SRC src.byte
#define SRC_RC0 src.bit._RC0
#define SRC_RC1 src.bit._RC1
#define SRC_RC2 src.bit._RC2
#define SRC_CS0 src.bit._CS0
#define SRC_CS1 src.bit._CS1
#define SRC_CR src.bit._CR
#define SRC_RC src.bitc._RC
#define SRC_CS src.bitc._CS

extern __io SSDSTR ssd;  
#define SSD ssd.byte
#define SSD_RD8RP ssd.bit._RD8RP
#define SSD_TD8TP ssd.bit._TD8TP
#define SSD_RIE ssd.bit._RIE
#define SSD_TIE ssd.bit._TIE
#define SSD_TDRE ssd.bit._TDRE
#define SSD_ORFE ssd.bit._ORFE
#define SSD_RDRF ssd.bit._RDRF

extern __io volatile IO_BYTE sidr;
#define SIDR sidr   

extern __io volatile IO_BYTE sodr;
#define SODR sodr   

extern __io UPCSTR upc;  
#define UPC upc.byte
#define UPC_PR0 upc.bit._PR0
#define UPC_PR1 upc.bit._PR1
#define UPC_PR2 upc.bit._PR2
#define UPC_PREN upc.bit._PREN
#define UPC_PR upc.bitc._PR

extern __io ADC1STR adc1;   /*  ADC */
#define ADC1 adc1.byte
#define ADC1_AD adc1.bit._AD
#define ADC1_ADMV adc1.bit._ADMV
#define ADC1_ADI adc1.bit._ADI
#define ADC1_ANS0 adc1.bit._ANS0
#define ADC1_ANS1 adc1.bit._ANS1
#define ADC1_ANS2 adc1.bit._ANS2
#define ADC1_ANS adc1.bitc._ANS

extern __io ADC2STR adc2;  
#define ADC2 adc2.byte
#define ADC2_EXT adc2.bit._EXT
#define ADC2_ADIE adc2.bit._ADIE
#define ADC2_ADCK adc2.bit._ADCK

extern __io volatile IO_BYTE addh;
#define ADDH addh   

extern __io volatile IO_BYTE addl;
#define ADDL addl   

extern __io ADENSTR aden;  
#define ADEN aden.byte
#define ADEN_ADE0 aden.bit._ADE0
#define ADEN_ADE1 aden.bit._ADE1
#define ADEN_ADE2 aden.bit._ADE2
#define ADEN_ADE3 aden.bit._ADE3
#define ADEN_ADE4 aden.bit._ADE4
#define ADEN_ADE5 aden.bit._ADE5
#define ADEN_ADE6 aden.bit._ADE6
#define ADEN_ADE7 aden.bit._ADE7

extern __io EIE2STR eie2;   /*  external interrupt - level */
#define EIE2 eie2.byte
#define EIE2_IE20 eie2.bit._IE20
#define EIE2_IE21 eie2.bit._IE21
#define EIE2_IE22 eie2.bit._IE22
#define EIE2_IE23 eie2.bit._IE23
#define EIE2_IE24 eie2.bit._IE24
#define EIE2_IE25 eie2.bit._IE25
#define EIE2_IE26 eie2.bit._IE26
#define EIE2_IE27 eie2.bit._IE27

extern __io EIF2STR eif2;  
#define EIF2 eif2.byte
#define EIF2_IF20 eif2.bit._IF20

extern __io SMRSTR smr;   /*  SIO */
#define SMR smr.byte
#define SMR_SST smr.bit._SST
#define SMR_BDS smr.bit._BDS
#define SMR_CKS0 smr.bit._CKS0
#define SMR_CKS1 smr.bit._CKS1
#define SMR_SOE smr.bit._SOE
#define SMR_SCKE smr.bit._SCKE
#define SMR_SIOE smr.bit._SIOE
#define SMR_SIOF smr.bit._SIOF
#define SMR_CKS smr.bitc._CKS

extern __io volatile IO_BYTE sdr;
#define SDR sdr   

extern __io SSELSTR ssel;   /*  UART/SIO Switch Register */
#define SSEL ssel.byte
#define SSEL_SSEL ssel.bit._SSEL

extern __io WRARH0STR wrarh0;   /*  Wild Register Function */
#define WRARH0 wrarh0.byte
#define WRARH0_RA08 wrarh0.bit._RA08
#define WRARH0_RA09 wrarh0.bit._RA09
#define WRARH0_RA10 wrarh0.bit._RA10
#define WRARH0_RA11 wrarh0.bit._RA11
#define WRARH0_RA12 wrarh0.bit._RA12
#define WRARH0_RA13 wrarh0.bit._RA13
#define WRARH0_RA14 wrarh0.bit._RA14
#define WRARH0_RA15 wrarh0.bit._RA15

extern __io WRARL0STR wrarl0;  
#define WRARL0 wrarl0.byte
#define WRARL0_RA00 wrarl0.bit._RA00
#define WRARL0_RA01 wrarl0.bit._RA01
#define WRARL0_RA02 wrarl0.bit._RA02
#define WRARL0_RA03 wrarl0.bit._RA03
#define WRARL0_RA04 wrarl0.bit._RA04
#define WRARL0_RA05 wrarl0.bit._RA05
#define WRARL0_RA06 wrarl0.bit._RA06
#define WRARL0_RA07 wrarl0.bit._RA07

extern __io WRDR0STR wrdr0;  
#define WRDR0 wrdr0.byte
#define WRDR0_RD00 wrdr0.bit._RD00
#define WRDR0_RD01 wrdr0.bit._RD01
#define WRDR0_RD02 wrdr0.bit._RD02
#define WRDR0_RD03 wrdr0.bit._RD03
#define WRDR0_RD04 wrdr0.bit._RD04
#define WRDR0_RD05 wrdr0.bit._RD05
#define WRDR0_RD06 wrdr0.bit._RD06
#define WRDR0_RD07 wrdr0.bit._RD07

extern __io WRARH1STR wrarh1;  
#define WRARH1 wrarh1.byte
#define WRARH1_RA08 wrarh1.bit._RA08
#define WRARH1_RA09 wrarh1.bit._RA09
#define WRARH1_RA10 wrarh1.bit._RA10
#define WRARH1_RA11 wrarh1.bit._RA11
#define WRARH1_RA12 wrarh1.bit._RA12
#define WRARH1_RA13 wrarh1.bit._RA13
#define WRARH1_RA14 wrarh1.bit._RA14
#define WRARH1_RA15 wrarh1.bit._RA15

extern __io WRARL1STR wrarl1;  
#define WRARL1 wrarl1.byte
#define WRARL1_RA00 wrarl1.bit._RA00
#define WRARL1_RA01 wrarl1.bit._RA01
#define WRARL1_RA02 wrarl1.bit._RA02
#define WRARL1_RA03 wrarl1.bit._RA03
#define WRARL1_RA04 wrarl1.bit._RA04
#define WRARL1_RA05 wrarl1.bit._RA05
#define WRARL1_RA06 wrarl1.bit._RA06
#define WRARL1_RA07 wrarl1.bit._RA07

extern __io WRDR1STR wrdr1;  
#define WRDR1 wrdr1.byte
#define WRDR1_RD00 wrdr1.bit._RD00
#define WRDR1_RD01 wrdr1.bit._RD01
#define WRDR1_RD02 wrdr1.bit._RD02
#define WRDR1_RD03 wrdr1.bit._RD03
#define WRDR1_RD04 wrdr1.bit._RD04
#define WRDR1_RD05 wrdr1.bit._RD05
#define WRDR1_RD06 wrdr1.bit._RD06
#define WRDR1_RD07 wrdr1.bit._RD07

extern __io WRENSTR wren;  
#define WREN wren.byte
#define WREN_EN00 wren.bit._EN00
#define WREN_EN01 wren.bit._EN01

extern __io PDR6STR pdr6;   /*  Port Data/Direction Registers Port 6+7 */
#define PDR6 pdr6.byte
#define PDR6_P60 pdr6.bit._P60
#define PDR6_P61 pdr6.bit._P61
#define PDR6_P62 pdr6.bit._P62

extern __io DDR6STR ddr6;  
#define DDR6 ddr6.byte
#define DDR6_D60 ddr6.bit._D60
#define DDR6_D61 ddr6.bit._D61

extern __io PUL6STR pul6;  
#define PUL6 pul6.byte
#define PUL6_PUL60 pul6.bit._PUL60
#define PUL6_PUL61 pul6.bit._PUL61
#define PUL6_PUL62 pul6.bit._PUL62

extern __io PDR7STR pdr7;  
#define PDR7 pdr7.byte
#define PDR7_P70 pdr7.bit._P70
#define PDR7_P71 pdr7.bit._P71
#define PDR7_P72 pdr7.bit._P72

extern __io DDR7STR ddr7;  
#define DDR7 ddr7.byte
#define DDR7_D70 ddr7.bit._D70
#define DDR7_D71 ddr7.bit._D71
#define DDR7_D72 ddr7.bit._D72

extern __io PUL7STR pul7;  
#define PUL7 pul7.byte
#define PUL7_PUL70 pul7.bit._PUL70
#define PUL7_PUL71 pul7.bit._PUL71
#define PUL7_PUL72 pul7.bit._PUL72

extern __io PUL0STR pul0;   /*  Pull-Up Setting Registers */
#define PUL0 pul0.byte
#define PUL0_PUL00 pul0.bit._PUL00
#define PUL0_PUL01 pul0.bit._PUL01
#define PUL0_PUL02 pul0.bit._PUL02
#define PUL0_PUL03 pul0.bit._PUL03
#define PUL0_PUL04 pul0.bit._PUL04
#define PUL0_PUL05 pul0.bit._PUL05
#define PUL0_PUL06 pul0.bit._PUL06
#define PUL0_PUL07 pul0.bit._PUL07

extern __io PUL3STR pul3;  
#define PUL3 pul3.byte
#define PUL3_PUL30 pul3.bit._PUL30
#define PUL3_PUL31 pul3.bit._PUL31
#define PUL3_PUL32 pul3.bit._PUL32
#define PUL3_PUL33 pul3.bit._PUL33
#define PUL3_PUL34 pul3.bit._PUL34
#define PUL3_PUL35 pul3.bit._PUL35
#define PUL3_PUL36 pul3.bit._PUL36
#define PUL3_PUL37 pul3.bit._PUL37

extern __io PUL5STR pul5;  
#define PUL5 pul5.byte
#define PUL5_PUL50 pul5.bit._PUL50

extern __io FMCSSTR fmcs;   /* Flash Memory Control Status Register */
#define FMCS fmcs.byte
#define FMCS_RDY fmcs.bit._RDY
#define FMCS_WE fmcs.bit._WE
#define FMCS_RDYINT fmcs.bit._RDYINT
#define FMCS_INTE fmcs.bit._INTE

extern __io volatile IO_BYTE ilr1;
#define ILR1 ilr1    /*  Interrupt Level Setting Registers */

extern __io volatile IO_BYTE ilr2;
#define ILR2 ilr2   

extern __io volatile IO_BYTE ilr3;
#define ILR3 ilr3   

extern __io volatile IO_BYTE ilr4;
#define ILR4 ilr4   

#endif