mb89201.asm

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;  FFMC-8L IO-MAP HEADER FILE      
;  ==========================      
;  SOFTUNE WORKBENCH FORMAT 
;  CREATED BY IO-WIZARD V2.16    
;  ***********************************************************
;                FUJITSU MICROELEKTRONICS EUROPE GMBH                 
;                Am Siebenstein 6-10, 63303 Dreieich          
;                Tel.:++49/6103/690-0,Fax - 122               
;                                                             
;  The following software is for demonstration purposes only. 
;  It is not fully tested, nor validated in order to fullfill 
;  its task under all circumstances. Therefore, this software 
;  or any part of it must only be used in an evaluation       
;  laboratory environment.                                    
;  This software is subject to the rules of our standard      
;  DISCLAIMER, that is delivered with our SW-tools (on the CD 
;  "Micros Documentation & Software V3.0" see "\START.HTM" or 
;  see our Internet Page -                                    
;  http://www.fujitsu-ede.com/products/micro/disclaimer.html  
;  ***********************************************************

 .PROGRAM MB89201
 .TITLE   MB89201

;------------------------
; IO-AREA DECLARATONS :
;------------------------


 .section IOBASE, IO, locate=0x0000

 .GLOBAL _pdr0,     _ddr0,     _sycc,     _stbc,     _wdtc,     _tbtc
 .GLOBAL _pdr3,     _ddr3,     _rsfr,     _pdr4,     _ddr4,     _out4
 .GLOBAL _pdr5,     _ddr5,     _rcr21,    _rcr22,    _rcr212,   _rcr23
 .GLOBAL _rcr24,    _rcr234,   _bzcr,     _tccr,     _tcr1,     _tcr0
 .GLOBAL _tdr1,     _tdr0,     _tcph,     _tcpl,     _tcr2,     _cntr
 .GLOBAL _comr,     _eic1,     _eic2,     _smc,      _src,      _ssd
 .GLOBAL _sidr,     _sodr,     _upc,      _adc1,     _adc2,     _addh
 .GLOBAL _addl,     _aden,     _eie2,     _eif2,     _smr,      _sdr
 .GLOBAL _ssel,     _wrarh0,   _wrarl0,   _wrdr0,    _wrarh1,   _wrarl1
 .GLOBAL _wrdr1,    _wren,     _pdr6,     _ddr6,     _pul6,     _pdr7
 .GLOBAL _ddr7,     _pul7,     _pul0,     _pul3,     _pul5,     _fmcs
 .GLOBAL _ilr1,     _ilr2,     _ilr3,     _ilr4

_pdr0   .res.b 1  ;0000  /*  Port Data/Direction Registers Port 0 */
PDR0    .equ 0x0000
_ddr0   .res.b 1  ;0001
DDR0    .equ 0x0001
 .org 0x0007
_sycc   .res.b 1  ;0007  /*  Clock Control Registers */
SYCC    .equ 0x0007
_stbc   .res.b 1  ;0008
STBC    .equ 0x0008
_wdtc   .res.b 1  ;0009
WDTC    .equ 0x0009
_tbtc   .res.b 1  ;000A
TBTC    .equ 0x000A
 .org 0x000C
_pdr3   .res.b 1  ;000C  /*  Port Data/Direction Registers Port 3 */
PDR3    .equ 0x000C
_ddr3   .res.b 1  ;000D
DDR3    .equ 0x000D
_rsfr   .res.b 1  ;000E  /*  Reset Flag Register */
RSFR    .equ 0x000E
_pdr4   .res.b 1  ;000F  /*  Port Data/Direction Registers Port 4+5 */
PDR4    .equ 0x000F
_ddr4   .res.b 1  ;0010
DDR4    .equ 0x0010
_out4   .res.b 1  ;0011
OUT4    .equ 0x0011
_pdr5   .res.b 1  ;0012
PDR5    .equ 0x0012
_ddr5   .res.b 1  ;0013
DDR5    .equ 0x0013
_rcr21   .res.b 1  ;0014  /*  12bit PPG */
RCR21    .equ 0x0014
_rcr22   .res.b 1  ;0015
RCR22    .equ 0x0015
 .org 0x0014
_rcr212   .res.b 2  ;0014
RCR212    .equ 0x0014
_rcr23   .res.b 1  ;0016
RCR23    .equ 0x0016
_rcr24   .res.b 1  ;0017
RCR24    .equ 0x0017
 .org 0x0016
_rcr234   .res.b 2  ;0016
RCR234    .equ 0x0016
_bzcr   .res.b 1  ;0018  /*  Buzzer Register */
BZCR    .equ 0x0018
_tccr   .res.b 1  ;0019  /*  Timer and Capture */
TCCR    .equ 0x0019
_tcr1   .res.b 1  ;001A
TCR1    .equ 0x001A
_tcr0   .res.b 1  ;001B
TCR0    .equ 0x001B
_tdr1   .res.b 1  ;001C
TDR1    .equ 0x001C
_tdr0   .res.b 1  ;001D
TDR0    .equ 0x001D
_tcph   .res.b 1  ;001E
TCPH    .equ 0x001E
_tcpl   .res.b 1  ;001F
TCPL    .equ 0x001F
_tcr2   .res.b 1  ;0020
TCR2    .equ 0x0020
 .org 0x0022
_cntr   .res.b 1  ;0022  /*  PWM Register */
CNTR    .equ 0x0022
_comr   .res.b 1  ;0023
COMR    .equ 0x0023
_eic1   .res.b 1  ;0024  /*  external interrupt - edge */
EIC1    .equ 0x0024
_eic2   .res.b 1  ;0025
EIC2    .equ 0x0025
 .org 0x0028
_smc   .res.b 1  ;0028  /*  UART */
SMC    .equ 0x0028
_src   .res.b 1  ;0029
SRC    .equ 0x0029
_ssd   .res.b 1  ;002A
SSD    .equ 0x002A
_sidr   .res.b 1  ;002B
SIDR    .equ 0x002B
 .org 0x002B
_sodr   .res.b 1  ;002B
SODR    .equ 0x002B
_upc   .res.b 1  ;002C
UPC    .equ 0x002C
 .org 0x0030
_adc1   .res.b 1  ;0030  /*  ADC */
ADC1    .equ 0x0030
_adc2   .res.b 1  ;0031
ADC2    .equ 0x0031
_addh   .res.b 1  ;0032
ADDH    .equ 0x0032
_addl   .res.b 1  ;0033
ADDL    .equ 0x0033
_aden   .res.b 1  ;0034
ADEN    .equ 0x0034
 .org 0x0036
_eie2   .res.b 1  ;0036  /*  external interrupt - level */
EIE2    .equ 0x0036
_eif2   .res.b 1  ;0037
EIF2    .equ 0x0037
 .org 0x0039
_smr   .res.b 1  ;0039  /*  SIO */
SMR    .equ 0x0039
_sdr   .res.b 1  ;003A
SDR    .equ 0x003A
_ssel   .res.b 1  ;003B  /*  UART/SIO Switch Register */
SSEL    .equ 0x003B
 .org 0x0040
_wrarh0   .res.b 1  ;0040  /*  Wild Register Function */
WRARH0    .equ 0x0040
_wrarl0   .res.b 1  ;0041
WRARL0    .equ 0x0041
_wrdr0   .res.b 1  ;0042
WRDR0    .equ 0x0042
_wrarh1   .res.b 1  ;0043
WRARH1    .equ 0x0043
_wrarl1   .res.b 1  ;0044
WRARL1    .equ 0x0044
_wrdr1   .res.b 1  ;0045
WRDR1    .equ 0x0045
_wren   .res.b 1  ;0046
WREN    .equ 0x0046
 .org 0x0060
_pdr6   .res.b 1  ;0060  /*  Port Data/Direction Registers Port 6+7 */
PDR6    .equ 0x0060
_ddr6   .res.b 1  ;0061
DDR6    .equ 0x0061
_pul6   .res.b 1  ;0062
PUL6    .equ 0x0062
_pdr7   .res.b 1  ;0063
PDR7    .equ 0x0063
_ddr7   .res.b 1  ;0064
DDR7    .equ 0x0064
_pul7   .res.b 1  ;0065
PUL7    .equ 0x0065
 .org 0x0070
_pul0   .res.b 1  ;0070  /*  Pull-Up Setting Registers */
PUL0    .equ 0x0070
_pul3   .res.b 1  ;0071
PUL3    .equ 0x0071
_pul5   .res.b 1  ;0072
PUL5    .equ 0x0072
 .org 0x0079
_fmcs   .res.b 1  ;0079  /* Flash Memory Control Status Register */
FMCS    .equ 0x0079
 .org 0x007B
_ilr1   .res.b 1  ;007B  /*  Interrupt Level Setting Registers */
ILR1    .equ 0x007B
_ilr2   .res.b 1  ;007C
ILR2    .equ 0x007C
_ilr3   .res.b 1  ;007D
ILR3    .equ 0x007D
_ilr4   .res.b 1  ;007E
ILR4    .equ 0x007E
  .end