📄 ixp425.rpt
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X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 2/52
Number of signals used by logic mapping into function block: 2
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 22 I/O I
\$Net00002_ 1 0 0 4 FB3_3 STD 31 I/O O
\$Net00003_ 1 0 0 4 FB3_4 STD 32 I/O O
(unused) 0 0 0 5 FB3_5 24 I/O I
(unused) 0 0 0 5 FB3_6 34 I/O
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 25 I/O I
(unused) 0 0 0 5 FB3_9 27 I/O I
(unused) 0 0 0 5 FB3_10 39 I/O
(unused) 0 0 0 5 FB3_11 33 I/O
(unused) 0 0 0 5 FB3_12 40 I/O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 35 I/O
(unused) 0 0 0 5 FB3_15 36 I/O
(unused) 0 0 0 5 FB3_16 42 I/O
(unused) 0 0 0 5 FB3_17 38 I/O
(unused) 0 0 0 5 FB3_18 (b)
Signals Used by Logic in Function Block
1: "\$Net00001_" 2: "\$Net00049_"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
\$Net00002_ X....................................... 1 1
\$Net00003_ .X...................................... 1 1
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 (b)
(unused) 0 0 0 5 FB4_2 43 I/O
(unused) 0 0 0 5 FB4_3 46 I/O
(unused) 0 0 0 5 FB4_4 47 I/O
(unused) 0 0 0 5 FB4_5 44 I/O
(unused) 0 0 0 5 FB4_6 49 I/O
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 45 I/O
(unused) 0 0 0 5 FB4_9 (b)
(unused) 0 0 0 5 FB4_10 51 I/O
(unused) 0 0 0 5 FB4_11 48 I/O
(unused) 0 0 0 5 FB4_12 52 I/O
(unused) 0 0 0 5 FB4_13 (b)
(unused) 0 0 0 5 FB4_14 50 I/O
(unused) 0 0 0 5 FB4_15 56 I/O
(unused) 0 0 0 5 FB4_16 (b)
(unused) 0 0 0 5 FB4_17 57 I/O
(unused) 0 0 0 5 FB4_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"\$Net00079_" = "\$Net00129_"
"\$Net00078_" = Gnd
"\$Net00003_" = "\$Net00049_"
"\$Net00002_" = "\$Net00001_"
"\$Net00073_" = "\$Net00019_"
/"\$Net00022_" = /"\$Net00051_" * /"\$Net00052_" * /"\$Net00031_" *
"\$Net00021_"
"\$Net00016_" = "\$Net00030_"
"\$Net00071_" = "\$Net00030_"
/"\$Net00080_" = /"\$Net00019_" * /"\$Net00029_"
/"\$Net00017_" = /"\$Net00051_" * /"\$Net00052_" * /"\$Net00031_" *
"\$Net00021_" * /"\$Net00029_"
**************************** Device Pin Out ****************************
Device : XC9572XL-10-VQ64
T T T T T T T G T T T V T T T T
I I I I I I I N I I I C I I I I
E E E E E E E D E E E C E E E E
-----------------------------------------------
/48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 \
TIE | 49 32 | \$Net00003_
TIE | 50 31 | \$Net00002_
TIE | 51 30 | TCK
TIE | 52 29 | TMS
TDO | 53 28 | TDI
GND | 54 27 | \$Net00031_
VCC | 55 26 | VCC
TIE | 56 XC9572XL-10-VQ64 25 | \$Net00030_
TIE | 57 24 | \$Net00029_
TIE | 58 23 | TIE
TIE | 59 22 | \$Net00019_
\$Net00071_ | 60 21 | GND
\$Net00073_ | 61 20 | TIE
\$Net00078_ | 62 19 | TIE
\$Net00079_ | 63 18 | TIE
\$Net00080_ | 64 17 | TIE
\ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 /
-----------------------------------------------
\ \ V T T \ \ \ \ \ \ \ T G T T
$ $ C I I $ $ $ $ $ $ $ I N I I
N N C E E N N N N N N N E D E E
e e e e e e e e e
t t t t t t t t t
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0
4 2 5 5 1 1 0 2 2
9 9 1 2 6 7 1 1 2
_ _ _ _ _ _ _ _ _
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9572XL-10-VQ64
Use Timing Constraints : ON
Ignore Assignments In Design File : OFF
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : OFF
Use Pin Feedback : OFF
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : OFF
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : ON
Global Set/Reset(GSR) Optimization : ON
Global Output Enable(GTS) Optimization : ON
Collapsing pterm limit : 25
Collapsing input limit : 54
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