📄 ixp425.rpt
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XACT: version D.19 Xilinx Inc.
Fitter Report
Design Name: ixp425 Date: 6-30-2005, 1:54PM
Device Used: XC9572XL-10-VQ64
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
10 /72 ( 13%) 9 /360 ( 2%) 0 /72 ( 0%) 20 /52 ( 38%) 12 /216 ( 5%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 10 10 | I/O : 18 28
Output : 10 10 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 1 1
GCK : 0 0 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 20 20
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 0
Non-registered Macrocell driving I/O 10
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 10 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 10 macrocells used (MC).
End of Resource Summary
**************************** Errors and Warnings *************************
WARNING:nd201 - Removing unused input(s) '\$Net00108_, \$Net00072_,
\$Net00075_, \$Net00066_, \$Net00064_, \$Net00065_, \$Net00063_, \$Net00062_,
\$Net00034_, \$Net00028_, \$Net00025_, \$Net00024_, \$Net00026_, \$Net00015_,
\$Net00027_, \$Net00023_, \$Net00018_, \$Net00014_, \$Net00013_, \$Net00123_,
\$Net00050_'. The input(s) are unused after optimization.
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
\$Net00002_ 1 1 FB3_3 STD FAST 31 I/O O
\$Net00003_ 1 1 FB3_4 STD FAST 32 I/O O
\$Net00016_ 1 1 FB1_2 STD FAST 8 I/O O
\$Net00017_ 1 5 FB1_5 STD FAST 9 I/O O
\$Net00022_ 1 4 FB1_3 STD FAST 12 I/O O
\$Net00071_ 1 1 FB2_2 STD FAST 60 I/O O
\$Net00073_ 1 1 FB2_5 STD FAST 61 I/O O
\$Net00078_ 0 0 FB2_6 STD FAST 62 I/O O
\$Net00079_ 1 1 FB2_8 STD FAST 63 I/O O
\$Net00080_ 1 2 FB2_9 STD FAST 64 GSR/I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
\$Net00001_ FB1_6 10 I/O I
\$Net00019_ FB3_2 22 I/O I
\$Net00021_ FB1_8 11 I/O I
\$Net00029_ FB3_5 24 I/O I
\$Net00030_ FB3_8 25 I/O I
\$Net00031_ FB3_9 27 I/O I
\$Net00049_ FB2_10 1 I/O I
\$Net00051_ FB2_15 6 I/O I
\$Net00052_ FB2_17 7 I/O I
\$Net00129_ FB2_11 2 GTS/I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 3 6 6 3 3/0 13
FB2 5 4 4 4 5/0 13
FB3 2 2 2 2 2/0 14
FB4 0 0 0 0 0/0 12
---- ----- ----- -----
10 9 10/0 52
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 6/48
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 (b)
\$Net00016_ 1 0 0 4 FB1_2 STD 8 I/O O
\$Net00022_ 1 0 0 4 FB1_3 STD 12 I/O O
(unused) 0 0 0 5 FB1_4 13 I/O
\$Net00017_ 1 0 0 4 FB1_5 STD 9 I/O O
(unused) 0 0 0 5 FB1_6 10 I/O I
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 11 I/O I
(unused) 0 0 0 5 FB1_9 15 GCK/I/O
(unused) 0 0 0 5 FB1_10 18 I/O
(unused) 0 0 0 5 FB1_11 16 GCK/I/O
(unused) 0 0 0 5 FB1_12 23 I/O
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 17 GCK/I/O
(unused) 0 0 0 5 FB1_15 19 I/O
(unused) 0 0 0 5 FB1_16 (b)
(unused) 0 0 0 5 FB1_17 20 I/O
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: "\$Net00021_" 3: "\$Net00030_" 5: "\$Net00051_"
2: "\$Net00029_" 4: "\$Net00031_" 6: "\$Net00052_"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
\$Net00016_ ..X..................................... 1 1
\$Net00022_ X..XXX.................................. 4 4
\$Net00017_ XX.XXX.................................. 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 4/50
Number of signals used by logic mapping into function block: 4
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 (b)
\$Net00071_ 1 0 0 4 FB2_2 STD 60 I/O O
(unused) 0 0 0 5 FB2_3 58 I/O
(unused) 0 0 0 5 FB2_4 59 I/O
\$Net00073_ 1 0 0 4 FB2_5 STD 61 I/O O
\$Net00078_ 0 0 0 5 FB2_6 STD 62 I/O O
(unused) 0 0 0 5 FB2_7 (b)
\$Net00079_ 1 0 0 4 FB2_8 STD 63 I/O O
\$Net00080_ 1 0 0 4 FB2_9 STD 64 GSR/I/O O
(unused) 0 0 0 5 FB2_10 1 I/O I
(unused) 0 0 0 5 FB2_11 2 GTS/I/O I
(unused) 0 0 0 5 FB2_12 4 I/O
(unused) 0 0 0 5 FB2_13 (b)
(unused) 0 0 0 5 FB2_14 5 GTS/I/O
(unused) 0 0 0 5 FB2_15 6 I/O I
(unused) 0 0 0 5 FB2_16 (b)
(unused) 0 0 0 5 FB2_17 7 I/O I
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: "\$Net00019_" 3: "\$Net00030_" 4: "\$Net00129_"
2: "\$Net00029_"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
\$Net00071_ ..X..................................... 1 1
\$Net00073_ X....................................... 1 1
\$Net00078_ ........................................ 0 0
\$Net00079_ ...X.................................... 1 1
\$Net00080_ XX...................................... 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
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