dec6713.c

对芯片ti6713的存储器的存储初时化程序。包括sdram和flash存储器。能够实现高所存储数据功能。

/*********************************************************************************
* DEC6713.C	v1.00	     							                            *
* Copyright	2003 by SEED Electronic Technology Ltd.
* All rights reserved. Property of SEED Electronic Technology Ltd.			                *
* Designed by:	Hongshuai.Li								                                *
*********************************************************************************/ 
#include <csl.h>
#include <csl_mcasp.h>
#include <csl_i2c.h>
#include <csl_emif.h>
#include <csl_pll.h>
#include <DEC6713.h>

/*Local software delay function*/
static void PLLdelay(int Count)
{
    volatile int i = Count;
    while(i--);
}

/********************************************************************************\
\*DEC6713_init()	-Initialize DEC6713 board.
\*Parameters: NO.
\*		
\*Return:No.
\********************************************************************************/

void DEC6713_init()
{
	/* Initealize the board APIs */
	EMIF_Config MyEMIFcfg0={
		0x30								|
		EMIF_FMKS(GBLCTL,NOHOLD,DISABLE)	|
		EMIF_FMKS(GBLCTL,CLK1EN,DISABLE)	|
		EMIF_FMKS(GBLCTL,CLK2EN,ENABLE),
		
		EMIF_FMKS(CECTL,WRSETUP,DEFAULT)	|
		EMIF_FMKS(CECTL,WRSTRB,DEFAULT)		|
		EMIF_FMKS(CECTL,WRHLD,DEFAULT)		|
		EMIF_FMKS(CECTL,RDSETUP,DEFAULT)	|
		EMIF_FMKS(CECTL,TA,OF(2))			|
		EMIF_FMKS(CECTL,RDSTRB,DEFAULT)		|
		EMIF_FMKS(CECTL,MTYPE,SDRAM32)		|
		EMIF_FMKS(CECTL,RDHLD,DEFAULT),
		
		EMIF_FMKS(CECTL, WRSETUP, OF(2))      |
        EMIF_FMKS(CECTL, WRSTRB, OF(8))       |
        EMIF_FMKS(CECTL, WRHLD, OF(2))        |
        EMIF_FMKS(CECTL, RDSETUP, OF(0))      |
        EMIF_FMKS(CECTL, TA, OF(2))           |
        EMIF_FMKS(CECTL, RDSTRB, OF(8))       |
        EMIF_FMKS(CECTL, MTYPE, ASYNC16)       |
        EMIF_FMKS(CECTL, RDHLD, OF(2)),
		/*EMIF_FMKS(CECTL, WRSETUP, OF(3))    |
        EMIF_FMKS(CECTL, WRSTRB, OF(11))    |
        EMIF_FMKS(CECTL, WRHLD, OF(4))      |
        EMIF_FMKS(CECTL, RDSETUP, OF(1))    |
        EMIF_FMKS(CECTL, TA, OF(3))         |
        EMIF_FMKS(CECTL, RDSTRB, OF(24))    |
        EMIF_FMKS(CECTL, MTYPE, ASYNC16)    |
        EMIF_FMKS(CECTL, RDHLD, OF(4)),*/
        
        EMIF_FMKS(CECTL, WRSETUP, OF(3))    |
        EMIF_FMKS(CECTL, WRSTRB, OF(11))    |
        EMIF_FMKS(CECTL, WRHLD, OF(4))      |
        EMIF_FMKS(CECTL, RDSETUP, OF(1))    |
        EMIF_FMKS(CECTL, TA, OF(3))         |
        EMIF_FMKS(CECTL, RDSTRB, OF(24))    |
        EMIF_FMKS(CECTL, MTYPE, ASYNC8)    |
        EMIF_FMKS(CECTL, RDHLD, OF(4)),
		
		EMIF_FMKS(CECTL, WRSETUP, OF(2))    |
        EMIF_FMKS(CECTL, WRSTRB, OF(10))    |
        EMIF_FMKS(CECTL, WRHLD, OF(2))      |
        EMIF_FMKS(CECTL, RDSETUP, OF(2))    |
        EMIF_FMKS(CECTL, TA, OF(2))         |
        EMIF_FMKS(CECTL, RDSTRB, OF(10))    |
        EMIF_FMKS(CECTL, MTYPE, ASYNC32)    |
        EMIF_FMKS(CECTL, RDHLD, OF(2)),
        
        EMIF_FMKS(SDCTL,SDBSZ,4BANKS)		|
        EMIF_FMKS(SDCTL,SDRSZ,12ROW)		|
        EMIF_FMKS(SDCTL,SDCSZ,8COL)			|
        EMIF_FMKS(SDCTL,RFEN,ENABLE)		|
        EMIF_FMKS(SDCTL,INIT,YES)			|
        EMIF_FMKS(SDCTL,TRCD,OF(1))			|
        EMIF_FMKS(SDCTL,TRP,OF(1))			|
        EMIF_FMKS(SDCTL,TRC,OF(6)),
        
        EMIF_FMKS(SDTIM, CNTR, OF(0))       |
        EMIF_FMKS(SDTIM, PERIOD, OF(1562)),
        
		EMIF_FMKS(SDEXT, WR2RD, OF(0))      |
        EMIF_FMKS(SDEXT, WR2DEAC, OF(2))    |
        EMIF_FMKS(SDEXT, WR2WR, OF(1))      |
        EMIF_FMKS(SDEXT, R2WDQM, OF(1))     |
        EMIF_FMKS(SDEXT, RD2WR, OF(0))      |
        EMIF_FMKS(SDEXT, RD2DEAC, OF(1))    |
        EMIF_FMKS(SDEXT, RD2RD, OF(0))      |
        EMIF_FMKS(SDEXT, THZP, OF(2))       |
        EMIF_FMKS(SDEXT, TWR, OF(1))        |
        EMIF_FMKS(SDEXT, TRRD, OF(0))       |
        EMIF_FMKS(SDEXT, TRAS, OF(4))       |
        EMIF_FMKS(SDEXT, TCL, OF(1))
        };
        
	/* Initialize PLL Registers */         
		/* Put PLL in bypass */
	PLL_bypass();
	PLLdelay(20);
	
		/* Reset PLL */
	PLL_reset();
	PLLdelay(20);
	
		/* Set main multiplier/divisor */
   	PLL_RSET(PLLM,12);						//25MHz×18=450MHz
   	PLL_RSET(PLLDIV0, PLL_PLLDIV0_RMK(1, 0));		//450MHz/1=450MHz
   	PLL_RSET(OSCDIV1, PLL_OSCDIV1_RMK(1, 0));		//25MHz/1=25MHz(CLKOUT3)
   
   		/* Set DSP clock */
   	PLL_RSET(PLLDIV1,PLL_PLLDIV1_RMK(1, 1));		//450MHz/2=225MHz
   	PLLdelay(20);
   
    	/* Set peripheral clock */
    PLL_RSET(PLLDIV2,PLL_PLLDIV2_RMK(1, 3));		//450MHz/4=112.5MHz(CLKOUT2)
    PLLdelay(20);
    
    	/* Set EMIF clock */
    PLL_RSET(PLLDIV3,PLL_PLLDIV3_RMK(1, 4));		//450MHz/5=90MHz(ECLKOUT)
    PLLdelay(20);
    
    	/* Take PLL out of reset */
    PLL_deassert();
    PLLdelay(1500);
    
    	/* Enalbe PLL */
    PLL_enable();
    PLLdelay(20);
   
   	/* Initialize EMIF */
    EMIF_config(&MyEMIFcfg0);
    
	/* Set CPLD registers to default state  */    
   	//DEC6713_cpld_rset(DEC6713_CTL_REG,0);   	
      	
}
/********************************************************************************\
\*Uint8 DEC6713_cpld_rget()		-Read CPLD register。
\*Parameters：
\*		regnum: The related register.

\*Return: The related register value.
\********************************************************************************/
   	

/********************************************************************************\
\* End of DEC6713.C *\
\********************************************************************************/